US 2003/0228735 A1 · MOSFET FABRICATION METHOD

Abstract

An FET is fabricated on an SOI substrate by the following processes. Openings are formed in laminated layers of a pad oxide film of about 5-10 nm and an oxidation-resistant nitride film of about 50-150 nm at positions where device isolation regions are to be provided. The substrate is irradiated by an ion implantation apparatus with at least one of Ar ions and Si ions with an implantation energy of 40-50 keV, and a dose of 1×1014 to 5×1015 cm−2. Field oxidation is then conducted to electrically separate adjacent devices. The regions of the substrate where the openings are formed become amorphous when irradiated, and the field oxidation is consequently enhanced. Hence, a thermal oxidation film having sufficient thickness can be obtained even at device isolation regions having isolation widths of 0.2 μm or less.

Claims16

Dependent claims

A method of fabricating a MOSFET, the method comprising:

(a) preparing an SOI substrate;
(b) depositing an oxide film on the SOI substrate;
(c) depositing a nitride film on the oxide film;
(d) forming an opening in the nitride film and oxide film at a predetermined region, at which a device isolation region is to be formed, by lithography for exposing a surface of the SOI substrate;
(e) irradiating the substantially the entire area of the SOI substrate with Ar ions;
(f) forming a field oxide film by dry oxidation;
and
(g) removing remaining portions of the nitride film and the oxide film.

5 more elements

Dependencies are inferred from the claim text.

Mosfet fabrication method

Life of this patent

Mosfet fabrication method

Life of this patent

Abstract

Claims16