Data output driver and data output method for minimizing data output time variations caused by data patterns

A data output driver having an input terminal and an output terminal, comprising:

• a first current path provided between the output terminal and an intermediate node when a data read operation is performed;
• a driver adapted to drive data that is input through the input terminal, to the output terminal through the intermediate node in the data read operation;
• and
• a second current path provided between the intermediate node and a lower supply voltage during the data read operation.

A data output driver adapted to drive data that is input through an input terminal, to an output terminal, comprising:

• an intermediate node;
• a first transistor connected between the output terminal and the intermediate node, the first transistor including a control terminal to which an enable signal is input;
• a second transistor connected between the intermediate node and a lower supply voltage, the second transistor including the input terminal through which the data is input;
• and
• a third transistor connected between the intermediate node and the lower supply voltage, the third transistor including a control terminal to which a control signal is input.

A data output driver comprising:

• an output terminal;
• an intermediate node;
• a first transistor connected between the output terminal and the intermediate node, and including a gate to which an enable signal is input;
• a second transistor connected between the intermediate node and a lower supply voltage, and including a gate to which data is input;
• and
• a third transistor connected between the intermediate node and the lower supply voltage, and comprising a gate to which a control signal is input.

A semiconductor memory device comprising a plurality of data output drivers for outputting data that are input through respective input terminals, to respective output terminals, wherein each of the plurality of data output drivers comprises:

• an intermediate node;
• a first transistor connected between one of the output terminals and the intermediate node, and including a gate to which an enable signal is input;
• a second transistor connected between the intermediate node and a lower supply voltage, and including a gate to which one of the plural data is input;
• and
• a third transistor connected between the intermediate node and the lower supply voltage, and comprising a gate to which a control signal is input.

A data output driver having an input terminal and an output terminal, comprising:

• an intermediate node;
• a first transistor connected between the output terminal and the intermediate node, the first transistor including a control terminal to which an enable signal is input;
• a second transistor connected between the intermediate node and a lower supply voltage, the second transistor adapted to discharge to the lower supply voltage a first current quantity according to data that is input to the input terminal;
• and
• a third transistor connected between the intermediate node and the lower supply voltage, the second transistor including a control terminal and being adapted to discharge to the lower supply voltage a second current quantity according to a control signal that is input to the control terminal thereof.