Shift register, liquid crystal display device having the shift register and method of driving scan lines using the same

The shift register of claim 4, wherein the dummy pull-up driver part comprises:

• a capacitor coupled between a first input node of the dummy pull-up part and the dummy output terminal;
• a first transistor, a first drain of the first transistor receiving the first power voltage, a first gate of the first transistor receiving the scan line driving signal of the previous stage, and a first source of the first transistor coupled to the first input node of the dummy pull-up part;
• a second transistor, a second drain of the second transistor coupled to the first input node of the dummy pull-up part, a second gate of the second transistor coupled to a second input node of the dummy pull-down part, and a second source of the second transistor receiving the first power voltage;
• and
• a third transistor, a third drain of the third transistor coupled to the first input node of the dummy pull-up part, a third gate of the third transistor coupled to an output terminal of the dummy pull-up part, and a third source of the third transistor receiving the first power voltage.

A liquid crystal display device comprising:

• a display cell array formed on a transparent substrate, the display cell array including a plurality of gate lines, a plurality of data lines and a plurality of switching elements, the switching elements respectively coupled to each of the data lines and each of the gate lines;
• a data driver circuit, coupled with the data lines, for providing the data lines with image signals;
• a gate driver circuit, coupled with the gate lines, for driving the switching elements, the gate driver circuit including i) a plurality of stages including odd numbered stages and even numbered stages, the odd numbered stages respectively receiving a first clock and a first control signal, the first clock being prevented from being outputted from each of the odd numbered stages in response to the first control signal, the even numbered stages respectively receiving a second clock and a second control signal, the second clock being prevented from being outputted from each of the even numbered stages in response to the second control signal, the second clock having a first phase 180° different from a second phase of the first clock, the stages respectively delaying the first clock or the second clock by a first period and sequentially outputting the first clock and the second clock as a gate line driving signal to sequentially select the gate lines, ii) a dummy stage for generating a dummy output signal, the gate line driving signal of a last stage falling below a first predetermined voltage level in response to the dummy output signal of the dummy stage, the dummy output signal being delayed by a second period and falling below a second predetermined voltage level in response to the dummy output signal.

A liquid crystal display device comprising:

• a display cell array formed on a transparent substrate, the display cell array including a plurality of gate lines, a plurality of data lines and a plurality of switching elements, the switching elements respectively coupled to each of the data lines and each of the gate lines;
• a data driver circuit, coupled with the data lines, for providing the data lines with image signals;
• a gate driver circuit, coupled with the gate lines, for driving the switching elements, the gate driver circuit including i) a plurality of stages including odd numbered stages and even numbered stages, the odd numbered stages respectively receiving a first clock and a first control signal, the first clock being prevented from being outputted from each of the odd numbered stages in response to the first control signal, the even numbered stages respectively receiving a second clock and a second control signal, the second clock being prevented from being outputted from each of the even numbered stages in response to the second control signal, the second clock having a first phase 180° different from a second phase of the first clock, the stages respectively delaying the first clock or the second clock by a first period to sequentially output the first clock and the second clock as a gate line driving signal, ii) a dummy stage, coupled to a last stage, for generating a dummy output signal, the gate line driving signal of the last stage falling below a first predetermined voltage level in response to the dummy output signal of the dummy stage, the dummy output signal being delayed by a second period and falling below a second predetermined voltage level in response to a control signal of the last stage.

A method of driving a plurality of scan lines by providing a display panel with a plurality of scan line driving signals, the method comprising:

• receiving a scan start signal to generate a first scan line driving signal and lowering a first voltage level of the first scan line driving signal so as to inactivate a first scan line in response to a second scan line driving signal;
• receiving a (N−1)th scan line driving signal to generate a Nth scan line driving signal and lowering a second voltage level of the Nth scan line driving signal so as to inactivate a Nth scan line in response to an (N+1)th scan line driving signal, N being a natural number more than 2;
• generating a Mth scan line driving signal in response to a (M−1)th scan line driving signal, M being the integer greater than N and having a same number as a number of the scan lines;
• generating a control signal in response to the Mth scan line driving signal and lowering a third voltage level of the Mth scan line driving signal so as to inactivate a Mth scan line;
• lowering a fourth voltage level of the control signal after a predetermined period of delay in response to the control signal.

A method of driving a plurality of scan lines by providing a display panel with a plurality of scan line driving signals, the method comprising:

• receiving a scan start signal to generate a first scan line driving signal and lowering a first voltage level of the first scan line driving signal so as to inactivate a first scan line in response to a second scan line driving signal;
• receiving a (N−1)th scan line driving signal to generate a Nth scan line driving signal and lowering a second voltage level of the Nth scan line driving signal so as to inactivate a Nth scan line in response to an (N+1)th scan line driving signal, N being a natural number more than 2;
• generating a Mth scan line driving signal in response to a (M−1)th scan line driving signal, M being the integer greater than N and having a same number as a number of the scan lines;
• generating a dummy output signal in response to the Mth scan line driving signal and lowering a third voltage level of the Mth scan line driving signal so as to inactivate a Mth scan line, the Mth scan line driving signal having a first voltage level;
• lowering a fourth voltage level of the dummy output signal in response to a control signal, the control signal having substantially the first voltage level.

A shift register including odd numbered stages and even numbered stages, the odd numbered stages respectively receiving a first clock, the even numbered stages respectively receiving a second clock having a first phase 180° different from a second phase of the first clock, the shift register comprising:

• a first stage performing a forward shift from the first stage to a last stage when a first selection signal has a first voltage level and performing a backward shift from the last stage to the first stage when a second selection signal has the first voltage level;
• a Nth stage performing the forward shift from the first stage to the last stage when the first selection signal has the first voltage level and performing the backward shift from the last stage to the first stage when the second selection signal has the first voltage level, N being an integer greater than or equal to 2;
• a last stage performing the forward shift from the first stage to the last stage when the first selection signal has the first voltage level and performing the backward shift from the last stage to the first stage when the second selection signal has the first voltage level;
• a first dummy stage for inactivating the last stage during the forward shift;
• and
• a second dummy stage for inactivating the first stage during the backward shift.

A shift register including odd numbered stages and even numbered stages, the odd numbered stages respectively receiving a first clock, the even numbered stages respectively receiving a second clock having a first phase 180° different from a second phase of the first clock, the stages of the shifter register being sequentially shifted in synchronization with the first and second clock signals in a forward direction and in a backward direction, the shift register comprising:

• a first stage receiving a scan start signal to generate a first scan line driving signal when a first selection signal has a first voltage level and lowering a second voltage level of the first scan line driving signal in response to a second scan line driving signal generated from a second stage, the first stage generating the first scan line driving signal in response to the second scan line driving signal when a second selection signal has the first voltage level and lowering the second voltage level of the first scan line driving signal in response to a second dummy output signal;
• a Nth stage generating a Nth scan line driving signal in response to a (N−1)th scan line driving signal outputted from a (N−1)th stage when the first selection signal has the first voltage level and lowering a third voltage level of the Nth scan line driving signal in response to an (N+1)th scan line driving signal outputted from an (N+1)th stage, the Nth stage generating the Nth scan line driving signal in response to the (N+1)th scan line driving signal when the second selection signal has the first voltage level and lowering the third voltage level of the Nth scan line driving signal in response to the (N−1)th scan line driving signal, N being an integer greater than 2;
• a Mth stage generating a. Mth scan line driving signal in response to a (M−1)th scan line driving signal outputted from a (M−1)th stage when the first selection signal has the first voltage level and lowering a fourth voltage level of the Mth scan line driving signal in response to a first dummy output signal, the Mth stage generating the Mth scan line driving signal in response to the scan start signal when the second selection signal has the first voltage level and lowering the fourth voltage level of the Mth scan line driving signal in response to the (M−1)th scan line driving signal, M being the integer greater than N;
• a first dummy stage receiving the first clock signal and the Mth scan line driving signal to generate the first dummy output signal, and the first dummy stage lowering a fifth voltage level of the first dummy output signal in response to the scan start signal;
• and
• a second dummy stage receiving the second clock signal and the first scan line driving signal to generate the second dummy output signal, and the second dummy stage lowering a sixth voltage level of the second dummy output signal in response to the scan start signal.

A liquid crystal display device comprising:

• a display cell array formed on a transparent substrate, the display cell array including a plurality of gate lines, a plurality of data lines and a plurality of switching elements, the switching elements respectively coupled to each of the data lines and each of the gate lines;
• a data driver circuit, coupled with the data lines, for providing the data lines with image signals;
• a gate driver circuit including odd numbered stages and even numbered stages, the odd numbered stages respectively receiving a first clock, the even numbered stages respectively receiving a second clock having a first phase 180° different from a second phase of the first clock, the gate driver circuit including:
• i) a first stage performing a forward shift from the first stage to a last stage when a first selection signal has a first voltage level and performing a backward shift from the last stage to the first stage when a second selection signal has the first voltage level;
• ii) a Nth stage performing the forward shift from the first stage to the last stage when the first selection signal has the first voltage level and performing the backward shift from the last stage to the first stage when the second selection signal has the first voltage level, N being an integer greater than or equal to 2;
• iii) a last stage performing the forward shift from the first stage to the last stage when the first selection signal has the first voltage level and performing the backward shift from the last stage to the first stage when the second selection signal has the first voltage level;
• iv) a first dummy stage for inactivating the last stage during the forward shift;
• and
• v) a second dummy stage for inactivating the first stage during the backward shift.

A liquid crystal display device comprising:

• a display cell array formed on a transparent substrate, the display cell array including a plurality of gate lines, a plurality of data lines and a plurality of switching elements, the switching elements respectively coupled to each of the data lines and each of the gate lines;
• a data driver circuit, coupled with the data lines, for providing the data lines with image signals;
• a gate driver circuit including odd numbered stages and even numbered stages, the odd numbered stages respectively receiving a first clock, the even numbered stages respectively receiving a second clock having a first phase 180° different from a second phase of the first clock, the stages of the shifter register being sequentially shifted in synchronization with the first and second clock signals in a forward direction and in a backward direction, the gate driver circuit including:
• i) a first stage receiving a scan start signal to generate a first gate line driving signal when a first selection signal has a first voltage level and lowering a second voltage level of the first scan line driving signal in response to a second gate line driving signal generated from a second stage, the first stage generating the first gate line driving signal in response to the second gate line driving signal when a second selection signal has the first voltage level and lowering the second voltage level of the first gate line driving signal in response to a second dummy output signal;
• ii) a Nth stage generating a Nth gate line driving signal in response to a (N−1)th gate line driving signal outputted from a (N−1)th stage when the first selection signal has the first voltage level and lowering a third voltage level of the Nth gate line driving signal in response to an (N+1)th gate line driving signal outputted from an (N+1)th stage, the Nth stage generating the Nth gate line driving signal in response to the (N+1)th gate line driving signal when the second selection signal has the first voltage level and lowering the third voltage level of the Nth gate line driving signal in response to the (N−1)th gate line driving signal, N being an integer greater than 2;
• iii) a Mth stage generating a Mth gate line driving signal in response to a (M−1)th gate line driving signal outputted from a (M−1)th stage when the first selection signal has the first voltage level and lowering a fourth voltage level of the Mth gate line driving signal in response to a first dummy output signal, and the Mth stage generating the Mth gate line driving signal in response to the scan start signal when the second selection signal has the first voltage level and lowering the fourth voltage level of the Mth gate line driving signal in response to the (M−1)th gate line driving signal, M being the integer greater than N;
• iv) a first dummy stage receiving the first clock signal and the Mth gate line driving signal to generate the first dummy output signal, and the first dummy stage lowering a fifth voltage level of the first dummy output signal in response to the scan start signal;
• and
• v) a second dummy stage receiving the second clock signal and the first gate line driving signal to generate the second dummy output signal, and the second dummy stage lowering a sixth voltage level of the second dummy output signal in response to the scan start signal.

A liquid crystal display device comprising:

• a first transparent substrate;
• a second transparent substrate facing the first transparent substrate;
• a liquid crystal layer interposed between the first and second transparent substrates;
• a display cell array formed on the first transparent substrate, the display cell array including a plurality of gate lines, a plurality of data lines and a plurality of first switching elements, the first switching elements respectively coupled to each of the data lines and each of the gate lines;
• a gate driver circuit, formed on the first transparent substrate, for performing a bi-directional shift operation in which the gate lines are selected sequentially in a forward direction or in a backward direction, the gate driver circuit including a plurality of stages, a first dummy stage and a second dummy stage, the first dummy stage lowering a first voltage level of a last gate line driving signal outputted from a last stage, the second dummy stage lowering a second voltage level of a first gate line driving signal outputted from a first stage and inactivating the first dummy stage;
• a data driver circuit, formed on the first transparent substrate, for providing the data lines an image signal, the date driver circuit including a shift register and a plurality of data line blocks, the data line blocks respectively having a plurality of second switching elements, a first electrode of each of the second switching elements coupled to a data input terminal, second electrodes of the second switching elements coupled to respective data lines, third electrodes of the second switching elements commonly coupled to respective block selection terminals, the shift register having a plurality of data stages cascade-connected to each other, a first data stage receiving a scan start signal for initiating a selection of the data line blocks, the data stages outputting an block selection signal so as to sequentially select each of the data line blocks;
• a flexible printed circuit board for providing the gate driver circuit and the data driver circuit with a control signal and the image signal, respectively, the flexible printed circuit including a control integrated circuit and a data driver integrated circuit mounted thereon.

A method of driving a plurality of scan lines, the scan lines being sequentially selected in a forward shift from a first scan line to a last scan line or in a backward shift from the last scan line to the first scan line, the method comprising:

• performing the forward shift to generate a first scan line driving signal when a first selection signal has a first voltage level and performing the backward shift to generate the first scan line driving signal when a second selection signal has the first voltage level;
• performing the forward shift to generate 2nd, 3rd, . . . , (N−1)th scan line driving signals when the first selection signal has the first voltage level and performing the backward shift to generate the 2nd, 3rd, . . . , (N−1)th scan line driving signals when the second selection signal has the first voltage level, N being an integer greater than 4;
• performing the forward shift to generate a Nth scan line driving signal when the first selection signal has the first voltage level and performing the backward shift to generate the Nth scan line driving signal when the second selection signal has the first voltage level;
• generating a first dummy output signal during the forward shift to lower a second voltage level of the Nth scan line driving signal;
• and
• generating a second dummy output signal during the backward shift to lower a third voltage level of the first scan line driving signal.

A method of driving a plurality of scan lines, the scan lines being sequentially selected in a forward shift from a first scan line to a last scan line or in a backward shift from the last scan line to the first scan line, the method comprising:

• generating a first scan line driving signal in response to a scan start signal and lowering a first voltage level of the first scan line driving signal in response to a second scan line driving signal so as to perform the forward shift when a first selection signal has a first level, and generating the first scan line driving signal in response to the second scan line driving signal and lowering the first voltage level of the first scan line driving signal in response to a second dummy output signal so as to perform the backward shift when a second selection signal has the first level;
• generating 2nd, 3rd, . . . , and (N−1)th scan line driving signals in response to a previous scan line driving signal and lowering a second voltage level of each of the 2nd, 3rd, . . . , and (N−1)th scan line driving signals in response to a next scan line driving signal so as to perform the forward shift when the first selection signal has the first level, and generating the 2nd, 3rd, . . . , and (N−1)th first scan line driving signals in response to the next scan line driving signal and lowering the second voltage level of each of the 2nd, 3rd, . . . , and (N−1)th scan line driving signals in response to the previous scan line driving signal so as to perform the backward shift when the second selection signal has the first level, N being an integer greater than 4;
• generating a Nth scan line driving signal in response to a (N−1)th scan line driving signal and lowering a third voltage level of the Nth scan line driving signal in response to the first dummy output signal so as to perform the forward shift when the first selection signal has the first level, and generating the Nth scan line driving signal in response to the scan start signal and lowering the third voltage level of the Nth scan line driving signal in response to the (N−1)th scan line driving signal so as to perform the backward shift when the second selection signal has the first level;
• generating the first dummy output signal in response to the Nth scan line driving signal and lowering the third voltage level of the Nth scan line driving signal in response to the first dummy output signal during the forward shift;
• lowering a fourth voltage level of the first dummy output signal;
• generating the second dummy output signal in response to the first scan line driving signal and lowering the first voltage level of the first scan line driving signal in response to the second dummy output signal during the backward shift;
• and
• lowering a fifth voltage level of the second dummy output signal.