Frequency synthesizer for reducing noise
AssigneeSamsung Electronics Co., Ltd.
InventorJung-Hyun Lee
Life of this patent
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Abstract
A fractional-N frequency synthesizer includes a first divider, a second divider, and a division ratio controller. The first divider receives and divides an oscillation frequency signal. The second divider receives a predetermined feedback frequency signal and divides the feedback frequency signal in response to a selection signal. The division ratio controller receives and divides an output signal of the first divider and an output signal of the second divider and generates a reference frequency signal in which the oscillation frequency signal is divided, a comparison frequency signal that is compared with the reference frequency signal, and the selection signal used to select the division ratio of the second divider.
Claims24
A frequency synthesizer comprising:
- a first divider adapted to receive and divide an oscillation frequency signal;
- a second divider adapted to receive a feedback frequency signal and divide the feedback frequency signal in response to a selection signal;
- and
- a division ratio controller adapted to receive and divide an output signal of the first divider and an output signal of the second divider, and adapted to generate a reference frequency signal in which the oscillation frequency signal is divided, a comparison frequency signal that is compared with the reference frequency signal, and the selection signal used to select the division ratio of the second divider.
A frequency synthesizer comprising:
- a first divider adapted to receive and divide an oscillation frequency signal;
- a second divider adapted to receive a predetermined feedback frequency signal and to divide the feedback frequency signal at various division ratios in response to a selection signal;
- a division ratio controller adapted to receive and divide an output signal of the first divider and an output signal of the second divider and to generate a reference frequency signal in which the oscillation frequency signal is divided, a comparison frequency signal that is compared with the reference frequency signal, and a first partial selection signal that is used to generate the selection signal used to select the division ratio of the second divider;
- and
- a sigma delta modulator adapted to receive a predetermined value K that is externally controlled and to generate a second partial selection signal used to generate the selection signal, in response to the comparison frequency signal.
A method for generating an output frequency signal of a desired range in a fractional-N frequency synthesizer having a sigma delta simulator, the method comprising:
- (a) dividing an oscillation frequency signal by R, dividing the R-divided oscillation frequency signal by D, and outputting a reference frequency signal;
- (b) receiving a feedback frequency signal and dividing the feedback frequency signal at various division ratios in response to a selection signal;
- (c) receiving and dividing the divided signal from (b), generating a comparison frequency signal that is compared with the reference frequency signal, and generating a first 1-bit selection signal used to generate the selection signal;
- (d) receiving a value K that is externally controlled and generating a second 1-bit selection signal used to generate the selection signal, in response to the comparison frequency signal;
- and
- (e) the selection signal generating from the first and second 1-bit selection signals.
Dependencies are inferred from the claim text.