Skewed bus driving method and circuit
AssigneeSamsung Electronics Co., Ltd.
InventorHoi-Jin Lee
Life of this patent
Estimating the term…
Abstract
Circuits and methods for driving buses (data buses or address buses) which provide a reduction in interference such as crosstalk between adjacent bus lines of a bus, even as the width of the bus increases and the intervals between the bus lines decrease. In the bus driving circuits and methods, a portion of the bus lines are driven at a first time, and a portion of the bus lines are driven at a second time, subsequent to the first time, so as to reduce or eliminate crosstalk between adjacent bus lines.
Claims25
A method for driving a bus comprising a plurality of bus lines, the method comprising the steps of:
- driving at a first time, each bus line that is to transmit a data bit having a first logic value;
- and
- driving at a second time which is subsequent to the first time, each bus line that is to transmit a data bit having a second logic value.
A method for driving a bus comprising a plurality of bus lines, the method comprising the steps of:
- driving a first set of alternating bus lines of the bus at a first time;
- and
- driving a second set of alternating bus lines of the bus at a second time that is subsequent to the first time
A method for driving a bus comprising a plurality of bus lines, the method comprising the steps of:
- determining whether a group of data bits loaded on three sequentially adjacent bus lines are [0, 1, 0];
- if the data bits are not [0, 1, 0], driving the three sequentially adjacent bus lines simultaneously without delay;
- and
- if the data bits are [0, 1, 0], driving the bus lines corresponding to the two most significant bits of the group of data bits at a first time, and driving the bus line corresponding to the least significant data bit of the group of data bits at a second time which is subsequent to the first time.
A circuit for driving a bus comprising a plurality of bus lines, the circuit comprising:
- a plurality of control circuits, wherein each control circuit is associated with a bus line and wherein each control circuit outputs a control signal comprising one of a driver enable signal and a delayed driver enable signal, based on a logic level of a data bit to be loaded on an associated bus line;
- and
- a plurality of drivers, wherein each driver is associated with a bus line and corresponding control circuit, and wherein each driver is responsive to the control signal output from a corresponding control circuit to drive an associated bus line.
A circuit for driving a bus comprising a plurality of bus lines, the circuit comprising:
- a delay element for delaying a driver enable signal for a predetermined time;
- a plurality of drivers, wherein each driver drives an associated bus line, wherein drivers associated with a first set of alternating bus lines receive the driver enable signal to drive the first set of alternating bus lines at a first time, and wherein drivers associated with a second set of alternating bus lines receive a delayed driver enable signal output from the delay element to drive the second set of alternating bus lines at a second time which is subsequent to the first time.
A circuit for driving a bus comprising a plurality of bus lines, the circuit comprising:
- a plurality of control circuits, wherein each control circuit outputs a driver enable signal without delay, if data bits loaded on three sequentially adjacent bus lines are not [0, 1, 0], and wherein each control circuit delays the driver enable signal for a predetermined time and then outputs a delayed driver enable signal, if the data bits loaded on the three sequentially adjacent bus lines are [0, 1, 0];
- and
- a plurality of drivers which drive corresponding bus lines in response to the output signals from the control circuits.
Dependencies are inferred from the claim text.