Programming circuit and method having extended duration programming capabilities

A memory device, comprising:

• a command decoder receiving memory command signals through externally accessible input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals;
• an address decoder receiving address signals through externally accessible input terminals, the address decoder generating row and column addressing signals responsive to the address signals;
• at least one memory array including a plurality of memory cells arranged in rows and columns, data being written to or read from the memory cells corresponding the address signals responsive to the memory control signals;
• a data path extending between a plurality of external terminals and the memory array for coupling data signals to and from the memory array;
• a plurality of programmable elements that are each programmed by coupling a programming current through the respective programmable element, the programmable elements being programmed to alter the operation of the memory device;
• and
• a programming circuit for selectively either isolating the programmable elements from one of the external terminals or allowing a programming voltage to be coupled from the external terminal to the programmable elements, the programming circuit comprising:
• an isolation device coupled between the external terminal and the programmable elements, the isolation device having a first terminal coupled to the external terminal, a second terminal coupled to the programmable elements, and control terminal, the isolation device being operable to couple the programming voltage applied to the external terminal to the programmable elements as long as the absolute value of the voltage coupled to the programmable elements is within a predetermined magnitude of a control voltage applied to the control terminal of the isolation device;
• and
• a charge pump circuit having a power input coupled to the external terminal and an output terminal coupled to the control terminal of the isolation device, the charge pump being coupled to receive the programming voltage applied to the external terminal and being operable in a program mode to increase the absolute value of the programming voltage in response to a program command signal to generate the control voltage, the charge pump circuit being operable in an isolation mode to generate as the control voltage a voltage having an absolute value that is substantially less than the absolute value of the programming voltage.

A computer system, comprising:

• an integrated circuit processor having a plurality of external terminals coupled to a processor bus;
• an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• and
• an integrated circuit memory device a plurality of external terminals coupled to the processor bus, the integrated circuit memory device comprising:
• a command decoder receiving memory command signals through externally accessible input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals;
• an address decoder receiving address signals through externally accessible input terminals, the address decoder generating row and column addressing signals responsive to the address signals;
• at least one memory array including a plurality of memory cells arranged in rows and columns, data being written to or read from the memory cells corresponding the address signals responsive to the memory control signals;
• a data path extending between a plurality of external terminals and the memory array for coupling data signals to and from the memory array;
• a plurality of programmable elements that are each programmed by coupling a programming current through the respective programmable element, the programmable elements being programmed to alter the operation of the memory device;
• and
• a programming circuit for selectively either isolating the programmable elements from one of the external terminals or allowing a programming voltage to be coupled from the external terminal to the programmable elements, the programming circuit comprising:
• an isolation device coupled between the external terminal and the programmable elements, the isolation device having a first terminal coupled to the external terminal, a second terminal coupled to the programmable elements, and control terminal, the isolation device being operable to couple the programming voltage applied to the external terminal to the programmable elements as long as the absolute value of the voltage coupled to the programmable elements is within a predetermined magnitude of a control voltage applied to the control terminal of the isolation device;
• and
• a charge pump circuit having a power input coupled to the external terminal and an output terminal coupled to the control terminal of the isolation device, the charge pump being coupled to receive the programming voltage applied to the external terminal and being operable in a program mode to increase the absolute value of the programming voltage in response to a program command signal to generate the control voltage, the charge pump circuit being operable in an isolation mode to generate as the control voltage a voltage having an absolute value that is substantially less than the absolute value of the programming voltage.

A method of supplying a voltage to a gate of a MOSFET transistor to allow the transistor to couple a programming voltage from an external terminal of an integrated circuit to a circuit ground to which a programming element may be coupled, the method comprising:

• coupling a drain of the MOSFET transistor to the external terminal;
• and
• coupling a source of the MOSFET transistor to the circuit ground;
• boosting the magnitude of the programming voltage to provide a boosted programming voltage;
• and
• applying the boosted programming voltage to a gate of the MOSFET transistor.

A method of programming a programmable element with a programming voltage in an integrated circuit in which the programmable element is coupled to a circuit ground node, the method comprising:

• when the programmable element is to be programmed:
• coupling an external terminal of the integrated circuit to the circuit ground node to the circuit ground node through a switching device having a control terminal;
• coupling a programming voltage to the external terminal;
• boosting the magnitude of the programming voltage to provide a boosted programming voltage;
• and
• applying the boosted programming voltage to the control terminal of the switching device to cause the switching device to couple the programming voltage to the programmable element;
• and
• when the programming element is not to be programmed, applying a voltage to the control terminal of the switching device to cause the switching device to isolate the circuit ground node from the external terminal.