Super high density module with integrated wafer level packages

An integrated wafer level package, comprising:

• at least two semiconductor dies disposed on a support substrate, each die comprising at least one bond pad;
• an insulating film overlying the dies, each of the bond pads exposed through openings in the film;
• and
• a redistribution layer comprising a plurality of traces and ball pads disposed on the insulating film, a trace interconnecting a bond pad of each of a first die and second die, and a trace connecting either the bond pad of the first die or the bond pad of the second die to a ball pad.

An integrated wafer level package, comprising:

• at least two semiconductor dies disposed on a support substrate, each die comprising one or more bond pads;
• an insulating film overlying the dies, the bond pads exposed through openings in the film;
• and
• a redistribution layer comprising a plurality of traces and ball pads disposed on the insulating film;
• a trace interconnecting a bond pad of a first die to the bond pad of a second die, and each bond pad of the dies being connected by a trace to a ball pad or to the bond pad of the other die which bond pad is connected by a trace to a ball pad.

An integrated wafer level package, comprising:

• a support substrate comprising two or more semiconductor dies, each die comprising a plurality of bond pads;
• an insulating film disposed over the dies, the film comprising openings aligned with and exposing the bond pads of the dies;
• and
• a plurality of traces and ball pads disposed on the insulating film;
• a trace connecting a bond pad of a first die to the bond pad of a second die, and a trace connecting each bond pad of the dies to a ball pad or to the bond pad of another die which bond pad is connected by a trace to a ball pad;
• and a trace connecting a bond pad of each of at least two of the two or more dies.

An integrated wafer level package, comprising:

• a support substrate comprising two or more semiconductor dies, each die comprising a plurality of bond pads;
• an insulating film disposed over the dies, the film comprising openings aligned with and exposing the bond pads of the dies;
• and
• a plurality of traces and ball pads disposed on the film;
• each bond pad of the dies being connected by a trace either to a ball pad or to a bond pad of the other die which bond pad is connected by a trace to a ball pad, and at least one trace connects the bond pads of at least two of the two or more dies.

An integrated wafer level package, comprising:

• a support substrate comprising at least first and second semiconductor dies, each die comprising a plurality of bond pads;
• an insulating film disposed over the dies, the film comprising openings aligned with and exposing the bond pads of the dies;
• and
• a plurality of traces and ball pads disposed on the insulating film;
• whereby a trace connects a bond pad of the first die to the ball pad, and a trace connects a bond pad of the second die to the bond pad of the first die.

An integrated wafer level package, comprising:

• a support substrate comprising at least first and second semiconductor dies, each die comprising a plurality of bond pads;
• an insulating film disposed over the dies, the film comprising openings aligned with and exposing the bond pads of the dies;
• and
• a redistribution layer comprising one or more ball pads and a plurality of traces disposed on the insulating film;
• one of the traces connecting a bond pad of the first die to one of the ball pads, and another of the traces connecting a bond pad of the second die to the bond pad of the first die.

An integrated wafer level package, comprising:

• a support substrate comprising at least three semiconductor dies, each die comprising a plurality of bond pads;
• an insulating film disposed over the dies with openings exposing the bond pads of the dies;
• and
• a plurality of traces and ball pads disposed on the insulating film;
• a bond pad of each of a first die and second die interconnected by a trace, and one of said bond pads of the first and second dies connected by a trace to a ball pad;
• an insulating layer disposed over the traces;
• and
• a plurality of traces disposed on the insulating layer;
• a bond pad of either the first die or the second die connected by a trace to a bond pad of a third die.

An integrated wafer level package, comprising:

• a support substrate comprising three or more semiconductor dies, each die comprising a plurality of bond pads;
• an insulating film disposed over the dies with openings exposing the bond pads of the dies;
• a plurality of traces and ball pads disposed on the insulating film;
• a bond pad of each of a first die and second die interconnected by a trace, and one of said bond pads of the first and second dies connected by a trace to a ball pad;
• an insulating layer disposed over the dies and comprising openings exposing the bond pads of the dies and the ball pads;
• and
• a plurality of traces disposed on the insulating layer;
• a bond pad of either the first die or the second die interconnected by a trace to a bond pad of a third die.

An integrated wafer level package, comprising:

• three or more dies disposed on a substrate, each of the dies comprising one or more bond pads;
• a first trace interconnecting a bond pad of each of a first and second die, and a second trace connecting one of said bond pads of the first and second dies to a ball pad;
• an insulating layer disposed over the first and second traces;
• the insulating layer having openings to expose the bond pads of the three or more dies and the ball pad;
• and
• a third trace disposed on the insulating layer and interconnecting a bond pad of either the first or second dies to a bond pad of the third die.

An integrated wafer level package, comprising:

• a support substrate comprising three or more semiconductor dies, each die comprising one or more bond pads;
• a bond pad of each of a first die and a second die interconnected by a trace;
• an insulating layer disposed over the dies and comprising openings exposing the bond pads of the dies;
• and
• a plurality of traces disposed on the insulating layer;
• a bond pad of either the first die or the second die interconnected by a trace to a bond pad of a third die;
• wherein one of said bond pads of the first, second or third dies is connected by a trace to a ball pad within the package.

An integrated wafer level package, comprising:

• a support substrate comprising three or more semiconductor dies, each die comprising one or more bond pads;
• an insulating film disposed over the substrate with openings exposing the bond pads of the dies;
• a first redistribution layer disposed on the insulating film and comprising traces;
• a bond pad of each of a first die and a second die interconnected by a trace;
• an insulating layer disposed over the first redistribution layer and comprising openings to the bond pads of the dies;
• and
• a second redistribution layer disposed on the insulating layer, and comprising one or more ball pads and a trace interconnecting a bond pad of either the first die or the second die to a bond pad of a third die, and a trace connecting said bond pad of the third die to the ball pad.

An integrated wafer level package, comprising:

• at least two dies disposed on a substrate;
• a first trace connecting a bond pad of two of the at least two dies;
• an insulating layer disposed over the first trace with an opening exposing the first trace;
• and
• a ball pad and a second trace disposed over the insulating layer, and a via interconnect disposed in the opening in contact with the first trace, and the second trace connecting the via interconnect to the ball pad.

An integrated wafer level package, comprising:

• a support substrate comprising two or more dies, each die comprising a plurality of bond pads;
• an insulating film disposed over the dies, the film comprising openings aligned with and exposing the bond pads of the dies;
• a plurality of first traces disposed on the insulating film, at least one of the first traces connecting a bond pad of a first die to the bond pad of a second die;
• an insulating layer disposed over the first traces with an opening exposing the at least one of the first traces;
• and
• a ball pad and a second trace disposed over the insulating layer, and a via interconnect disposed in the opening in contact with the at least one of the first traces, and the second trace connecting the via interconnect to the ball pad.

A semiconductor wafer, comprising:

• a substrate comprising one or more wafer level packages, each package comprising two or more semiconductor dies, and each die comprising a plurality of bond pads;
• an insulating film disposed over the substrate with openings exposing the bond pads of the dies;
• a plurality of traces and ball pads disposed on the insulating film;
• a bond pad of each of a first die and a second die within a package interconnected by a trace, and one of said bond pads of the first and second dies connected by a trace to a ball pad within the package.

A semiconductor wafer, comprising:

• a substrate comprising a plurality of wafer level packages, each package comprising two or more semiconductor dies, and each die comprising a plurality of bond pads;
• an insulating film overlying the substrate, the bond pads of the dies exposed through openings in the film;
• and
• a redistribution layer comprising a plurality of traces and ball pads disposed on the insulating film, a trace interconnecting a bond pad of each of a first and second die within each package, and a trace connecting one of said bond pads of the first and second dies to a ball pad within each package.

A semiconductor wafer, comprising:

• a substrate comprising a plurality of wafer level packages, each package comprising three or more semiconductor dies, and each die comprising a plurality of bond pads;
• an insulating film disposed over the dies with openings exposing the bond pads of the dies;
• a first plurality of traces and ball pads disposed on the insulating film, including a trace interconnecting a bond pad of each of a first die and a second die of at least one package, and a trace connecting one of said bond pads of the first and second dies to a ball pad within the package;
• an insulating layer disposed over the first plurality of traces with openings to the bond pads of the dies and the ball pads;
• and
• a second plurality of traces disposed on the insulating layer, including a trace interconnecting a bond pad of the first die or the second die of the package to a bond pad of a third die of the package.

A semiconductor wafer, comprising:

• a substrate comprising a plurality of wafer level packages, each package comprising four or more semiconductor dies, and each die comprising a plurality of bond pads;
• an insulating film disposed over the substrate with openings to the bond pads of the dies;
• a first set of traces and ball pads disposed on the insulating film, including a trace interconnecting a bond pad of each of a first die and a second die of at least one package, a trace connecting one of said bond pads of the first and second dies to a ball pad within the package, a trace interconnecting a bond pad of each of a third die and a fourth die of the package, and a trace connecting one of said bond pads of the third and fourth dies to a ball pad within the package;
• an insulating layer disposed over the first set of traces with openings to the bond pads of the dies and the ball pads;
• and
• a second set of traces disposed on the insulating layer, including traces interconnecting bond pads of the first and second dies to the third and fourth dies within the package.

A semiconductor wafer, comprising:

• a substrate comprising a plurality of wafer level packages, each package comprising three or more semiconductor dies, and each die comprising one or more bond pads;
• a bond pad of each of a first die and a second die interconnected by a trace;
• an insulating layer disposed over the dies and comprising openings exposing the bond pads of the dies;
• and
• a plurality of traces disposed on the insulating layer, including a trace interconnecting a bond pad of either the first die or the second die of each package to a bond pad of a third die of the package;
• wherein one of said bond pads of the first, second or third dies is connected by a trace to a ball pad within the package.

A semiconductor wafer, comprising:

• a support substrate comprising a plurality of wafer level packages, each package comprising three or more semiconductor dies, and each die comprising one or more bond pads;
• an insulating film disposed over the substrate with openings exposing the bond pads of the dies;
• a first redistribution layer disposed on the insulating film and comprising traces;
• a bond pad of each of a first die and a second die of at least one package interconnected by a trace;
• an insulating layer disposed over the dies and comprising openings exposing the bond pads of the dies;
• and
• a second redistribution layer disposed on the insulating layer, and comprising traces and one or more ball pads;
• a bond pad of either the first die or the second die of the package interconnected by a trace of the second redistribution layer to a bond pad of a third die of the package, and said bond pad of the third die is connected by a trace of the second redistribution layer to a ball pad.

A semiconductor wafer, comprising:

• a support substrate comprising two or more wafer level packages, each package comprising two or more dies, and each die comprising a plurality of bond pads;
• an insulating film disposed over the substrate with openings exposing the bond pads of the dies;
• a plurality of first traces disposed on the insulating film, a bond pad of each of a first die and a second die within each package interconnected by a trace;
• an insulating layer disposed over the first traces with an opening exposing each of the first traces;
• and
• a plurality of ball pads and second traces disposed over the insulating layer, and a via interconnect disposed in each of the openings in contact with at least one of the first traces, and at least one of the second traces connecting the via interconnect to at least one ball pad.

An electronic system, comprising:

• an integrated circuit module comprising at least one wafer level package, the package comprising at least three semiconductor dies disposed on a substrate, each die comprising at least one bond pad;
• an insulating film disposed over the dies with openings to the bond pads of the dies;
• and a plurality of traces and ball pads disposed on the insulating film, a bond pad of each of a first die and second die interconnected by a trace, and one of said bond pads of the first and second dies connected by a trace to a ball pad;
• an insulating layer disposed over the traces;
• and a plurality of traces disposed on the insulating layer, including a trace interconnecting a bond pad of either the first die or the second die to a bond pad of a third die.

An electronic system, comprising:

• an integrated circuit module comprising at least one wafer level package, the package comprising three or more semiconductor dies, each die comprising one or more bond pads;
• a bond pad of each of a first die and a second die interconnected by a trace;
• an insulating layer disposed over the dies and comprising openings exposing the bond pads of the dies;
• and a plurality of traces disposed on the insulating layer, including a trace interconnecting a bond pad of either the first or the second die to a bond pad of a third die;
• wherein one of said bond pads of the first, second or third dies connected by a trace to a ball pad.

An electronic system, comprising:

• an integrated circuit module comprising at least one wafer level package, each package comprising three or more semiconductor dies, and each die comprising one or more bond pads;
• an insulating film disposed over the dies with openings to the bond pads of the dies;
• a first redistribution layer disposed on the insulating film and comprising a trace interconnecting a bond pad of each of a first die and second die of a package;
• an insulating layer disposed over the first redistribution layer and comprising openings to the bond pads of the dies;
• and a second redistribution layer disposed on the insulating layer, and comprising one or more ball pads and a trace interconnecting said bond pad of either the first die or the second die of the package to a bond pad of a third die of the package, and a trace connecting said bond pad of the third die to the ball pad within the package.

An electronic system, comprising:

• an integrated circuit module comprising at least one wafer level package, the package comprising at least two semiconductor dies disposed on a substrate, each die comprising at least one bond pad;
• an insulating film overlying the dies, each of the bond pads exposed through openings in the film;
• a first redistribution layer comprising a plurality of traces disposed on the insulating film, a trace interconnecting a bond pad of each of a first die and second die;
• an insulating layer overlying the first redistribution layer with an opening exposing each of the traces of the first redistribution layer;
• and a second redistribution layer comprising a plurality of ball pads and traces disposed on the insulating layer, and a via interconnect disposed in each of the openings in contact with the trace of the first redistribution layer, and at least one of the traces of the second redistribution layer connecting the via interconnect to at least one ball pad.

A memory module, comprising:

• a printed circuit board;
• and
• an integrated circuit module comprising at least one wafer level package, the package comprising at least two semiconductor dies disposed on a substrate, each die comprising at least one bond pad;
• an insulating film overlying the dies, each of the bond pads exposed through openings in the film;
• and a redistribution layer comprising a plurality of traces and ball pads disposed on the insulating film, a trace interconnecting a bond pad of each of a first die and second die, and a trace connecting either the bond pad of the first die or the bond pad of the second die to a ball pad.

A memory module, comprising:

• a printed circuit board;
• and
• an integrated circuit module comprising at least one wafer level package, the package comprising at least one wafer level package, the package comprising at least three semiconductor dies disposed on a substrate, each die comprising at least one bond pad;
• an insulating film disposed over the dies with openings to the bond pads of the dies;
• and a plurality of traces and ball pads disposed on the insulating film, a bond pad of each of a first die and second die interconnected by a trace, and one of said bond pads of the first and second dies connected by a trace to a ball pad;
• an insulating layer disposed over the traces;
• and a plurality of traces disposed on the insulating layer, including a trace interconnecting a bond pad of either the first die or the second die to a bond pad of a third die.

A memory module, comprising:

• a printed circuit board;
• and
• an integrated circuit module comprising at least one wafer level package, the package comprising three or more semiconductor dies, each die comprising one or more bond pads;
• a bond pad of each of a first die and a second die interconnected by a trace;
• an insulating layer disposed over the dies and comprising openings exposing the bond pads of the dies;
• and a plurality of traces disposed on the insulating layer;
• a bond pad of either the first or the second die interconnected by a trace to a bond pad of a third die;
• wherein one of said bond pads of the first, second or third dies is connected by a trace to a ball pad.

A memory module, comprising:

• a printed circuit board;
• and
• an integrated circuit module comprising at least one wafer level package, each package comprising three or more semiconductor dies, and each die comprising one or more bond pads;
• an insulating film disposed over the dies with openings to the bond pads of the dies;
• a first redistribution layer disposed on the insulating film and comprising a trace interconnecting a bond pad of each of a first die and second die of a package;
• an insulating layer disposed over the first redistribution layer and comprising openings to the bond pads of the dies;
• and a second redistribution layer disposed on the insulating layer, and comprising one or more ball pads and a trace interconnecting said bond pad of either the first die or the second die of the package to a bond pad of a third die of the package, and a trace connecting said bond pad of the third die to the ball pad within the package.

A memory module, comprising:

• a printed circuit board;
• and
• an integrated circuit module comprising at least one wafer level package, the package comprising at least two semiconductor dies disposed on a substrate, each die comprising at least one bond pad;
• an insulating film overlying the dies, each of the bond pads exposed through openings in the film;
• a first redistribution layer comprising a plurality of traces disposed on the insulating film, a trace interconnecting a bond pad of each of a first die and second die;
• an insulating layer overlying the first redistribution layer with an opening exposing each of the traces of the first redistribution layer;
• and a second redistribution layer comprising a plurality of ball pads and traces disposed on the insulating layer, and a via interconnect disposed each of the openings in contact with the trace of the first redistribution layer, and at least one of the traces of the second redistribution layer connecting the via interconnect to at least one ball pad.

A method of fabricating a wafer level package, comprising the steps of:

• providing a substrate having a plurality of semiconductor dies formed thereon;
• each die comprising one or more bond pads;
• applying an insulating film over the substrate,
• forming openings through the insulating film to the bond pads of the dies;
• and
• forming a redistribution layer over the insulating film, the redistribution layer comprising a plurality of traces and ball pads;
• a trace interconnecting a bond pad of each of a first die and a second die, and a trace connecting one of the bond pads of the first and second dies to a ball pad.

A method of fabricating a wafer level package, comprising the steps of:

• providing a substrate having at least three semiconductor dies formed thereon;
• each die comprising at least one bond pad;
• applying an insulating film over the dies;
• forming openings through the insulating film to the bond pads of the dies;
• and
• forming a plurality of traces and ball pads over the insulating film, wherein a trace interconnects a bond pad of each of a first die and a second die, and a trace connects one of the bond pads of the first and second dies to a ball pad;
• applying an insulating layer over the traces;
• and
• forming a plurality of traces over the insulating layer, wherein a trace interconnects a bond pad of either the first die or the second die to a bond pad of a third die.

A method of fabricating a wafer level package, comprising the steps of:

• providing a substrate having at least three semiconductor dies formed thereon;
• each die comprising one or more bond pads, and a trace interconnecting a bond pad of each of a first die and a second die;
• applying an insulating layer over the traces;
• forming openings through the insulating layer to the bond pads of the dies;
• and
• forming a plurality of traces and ball pads over the insulating layer, wherein a trace interconnects a bond pad of either the first or the second die to a bond pad of a third die;
• wherein a trace connects one of said bond pads of the first, second or third dies to a ball pad.

A method of fabricating a wafer level package, comprising the steps of:

• providing a substrate comprising three or more semiconductor dies;
• each die comprising one or more bond pads, an insulating film disposed over the dies with openings to the bond pads of the dies;
• forming a first redistribution layer on the insulating film, the first redistribution layer comprising a plurality of traces, wherein a trace interconnects a bond pad of each of a first die and a second die;
• applying an insulating layer over the first redistribution layer;
• forming openings through the insulating layer to the bond pads of the dies;
• and
• forming a second redistribution layer on the insulating layer, the second redistribution layer comprising one or more ball pads and a trace interconnecting a bond pad of either the first or the second die to a bond pad of a third die, and a trace connecting said bond pad of the third die to a ball pad.

A method of forming a die package on a wafer level, comprising:

• providing a semiconductor wafer having a plurality of semiconductor dies disposed thereon;
• forming an insulating film over the wafer, the film having openings to the bond pads of the dies;
• and
• forming a redistribution layer on the insulating film to form a plurality of ball pads and traces, including a trace connecting a bond pad of each of a first die and a second die, and a trace connecting one of said bond pads of the first and second dies to a ball pad.

A method of forming a die package on a wafer level, comprising:

• forming a first redistribution layer over at least two dies disposed on a substrate, the first redistribution layer comprising a plurality of traces including a trace connecting a bond pad of each of the two dies;
• forming an insulating layer over the first redistribution layer;
• forming openings through the insulating layer to expose each of the traces of the first redistribution layer;
• and
• forming a second redistribution layer over the insulating layer, the second redistribution layer comprising a plurality of ball pads and traces, and a via interconnect disposed in each of the openings of the insulating layer in contact with a trace of the first redistribution layer, and a trace of the second redistribution layer connecting the via interconnect to at least one ball pad.

A method of fabricating an integrated circuit module, comprising the steps of:

• providing a substrate comprising a plurality of wafer level packages, each package comprising at least two semiconductor dies, each die having at least one bond pad;
• an insulating film overlying the dies with openings to the bond pads;
• and a redistribution layer comprising a plurality of traces and ball pads disposed on the insulating film, a trace interconnecting a bond pad of each of a first die and second die, and a trace connecting either the bond pad of the first die or the bond pad of the second die to a ball pad;
• separating each package on the substrate to form individual packages;
• and
• assembling one or more packages into an integrated circuit module.

A method of fabricating an integrated circuit module, comprising the steps of:

• providing a substrate comprising a plurality of wafer level packages, each package comprising at least three semiconductor dies, each die comprising at least one bond pad;
• an insulating film overlying the dies with openings to the bond pads;
• and a plurality of traces and ball pads disposed on the insulating film, a trace interconnecting a bond pad of each of a first die and second die, and a trace connecting either the bond pad of the first die or the bond pad of the second die to a ball pad;
• an insulating layer disposed over the traces;
• and a plurality of traces disposed on the insulating layer, with a trace interconnecting a bond pad of either the first die or the second die to a bond pad of a third die;
• separating each package on the substrate to form an individual package;
• and
• assembling one or more packages into an integrated circuit module.

A method of fabricating an integrated circuit module, comprising the steps of:

• providing a substrate comprising a plurality of wafer level packages, each package comprising three or more semiconductor dies, each die comprising one or more bond pads;
• a bond pad of each of a first die and a second die interconnected by a trace;
• an insulating layer disposed over the dies with openings to the bond pads of the dies;
• and a plurality of traces disposed on the insulating layer, with a trace interconnecting a bond pad of either the first or the second die to a bond pad of a third die;
• wherein one of said bond pads of the first, second or third dies connected by a trace to a ball pad;
• separating each package on the substrate to form an individual package;
• and
• assembling one or more packages into an integrated circuit module.

A method of fabricating an integrated circuit module, comprising the steps of:

• providing a substrate comprising a plurality of wafer level packages, each package comprising three or more semiconductor dies, each die comprising one or more bond pads;
• an insulating film disposed over the dies with openings to the bond pads;
• a first redistribution layer disposed on the insulating film and comprising traces, a bond pad of each of a first die and second die interconnected by a trace;
• an insulating layer disposed over the first redistribution layer and comprising openings to the bond pads of the dies;
• and a second redistribution layer disposed on the insulating layer, and comprising one or more ball pads, and a trace interconnecting a bond pad of either the first die or the second die to a bond pad of a third die;
• a trace connecting said bond pad of the third die to the ball pad;
• separating each package on the substrate to form an individual package;
• and
• assembling one or more packages into an integrated circuit module.

A method of fabricating an integrated circuit module, comprising the steps of:

• providing a substrate comprising a plurality of wafer level packages, each package comprising at least two semiconductor dies disposed, each die having at least one bond pad;
• an insulating film overlying the dies with openings to the bond pads;
• a first redistribution layer comprising a plurality of traces disposed on the insulating film, a trace interconnecting a bond pad of each of a first die and second die;
• an insulating layer overlying the first redistribution layer with an opening exposing each of the traces of the first redistribution layer;
• and a second redistribution layer comprising a plurality of ball pads and traces disposed on the insulating layer, and a via interconnect disposed in each of the openings in contact with the trace of the first redistribution layer, and a trace of the second redistribution layer connecting the via interconnect to at least one ball pad;
• separating each package on the substrate to form individual packages;
• and
• assembling one or more packages into an integrated circuit module.