Method and system for compression of address tags in memory structures

Abstract

A memory structure of a computer system receives an address tag associated with a computational value, generates a modified address which corresponds to the address tag using a compression function, and stores the modified address as being associated with the computational value. The address tag can be a physical address tag or a virtual address tag. The computational value (i.e., operand data or program instructions) may be stored in the memory structure as well, such as in a cache associated with a processing unit of the computer system. For such an implementation, the compressed address of a particular cache operation is compared to existing cache entries to determine which a cache miss or hit has occurred. In another exemplary embodiment, the memory structure is a memory disambiguation buffer associated with at least one processing unit of the computer system, and the compressed address is used to resolve load/store collisions. Compression may be accomplished using various encoding schemes, including complex schemes such as Huffinan encoding, or more elementary schemes such as differential encoding. The compression of the address tags in the memory structures allows for a smaller tag array in the memory structure, reducing the overall size of the device, and further reducing power consumption.

Dependencies are inferred from the claim text.