US 2003/0225985 A1 · Interleaver for iterative decoder

Abstract

Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implemented within communication devices that implement two distinct SISOs that operate cooperatively or within communication devices that employ a single SISO (in a recycled embodiment) that functionally performs the analogous decoding operations that would be performed by the two distinct SISO implementation. The use of single plane/single port memory devices by the interleaver allows for a great deal of savings from many perspectives: the sizes of the required interleaver memory and the interleaver pattern memory are both cut in half using this approach, and a cost savings may also be realized, in that, cheaper, slower memories may be used since each respective interleaver memory is read only every other cycle.

Claims47

Dependent claims

An interleaver memory structure for facilitating the decoding of a plurality of encoded symbols, the interleaver memory structure comprising:

during a first clock cycle:
a first interleaver pattern memory receives a first sequential read address;
a second interleaver pattern memory receives a first sequential write address;
during a second clock cycle:
the first interleaver pattern memory receives a second sequential write address;
the second interleaver pattern memory receives a second sequential read address;
a first read address is received from the first interleaver pattern memory for use by a first interleaver memory;
a first write address is received from the second interleaver pattern memory for use by a second interleaver memory;
during a third clock cycle:
the first interleaver pattern memory receives a third sequential read address;
the second interleaver pattern memory receives a third sequential write address;
a second write address is received from the first interleaver pattern memory for use by the first interleaver memory;
a second read address is received from the second interleaver pattern memory for use by the second interleaver memory;
a first data is read from the first interleaver memory;
a second data is written to the second interleaver memory;
and
wherein each of the first interleaver pattern memory, the second interleaver pattern memory, the first interleaver memory, and the second interleaver memory are implemented using single port memory structures.

14 more elements

An interleaver memory structure for facilitating the decoding of a plurality of encoded symbols, the interleaver memory structure comprising:

a first multiplexor (MUX) that receives the sequential read addresses and the sequential write addresses as inputs, the selection of the first MUX is made using a clock signal having even and odd cycles;
a second MUX that receives sequential read addresses and sequential write addresses as inputs, the selection of the second MUX is made using an inversion of the clock signal having even and odd cycles;
wherein corresponding sequential read addresses and sequential write addresses are offset by an odd value;
a first interleaver pattern memory that alternatively receives sequential read addresses and sequential write addresses from the first MUX;
a second interleaver pattern memory that alternatively receives sequential write addresses and sequential read addresses from the second MUX;
a first interleaver memory that is communicatively coupled to the first interleaver pattern memory;
a second interleaver memory that is communicatively coupled to the second interleaver pattern memory;
wherein the first interleaver memory receives input data that is written therein according to a sequential write address provided by the first interleaver pattern memory;
wherein the first interleaver memory provides output data that is read there from according to a sequential read address provided by the first interleaver pattern memory;
wherein the second interleaver memory receives input data that is written therein according to a sequential write address provided by the second interleaver pattern memory;
wherein the second interleaver memory provides output data that is read there from according to a sequential read address provided by the second interleaver pattern memory;
a third MUX that receives the output data from the first interleaver memory and the output data from the second interleaver memory as inputs, the selection of the third MUX is made using the clock signal having even and odd cycles;
and
wherein each of the first interleaver pattern memory, the second interleaver pattern memory, the first interleaver memory, and the second interleaver memory are implemented using single port memory structures.

11 more elements

A soft-in soft-out (SISO) decoder that includes an interleaver memory structure for facilitating the decoding of a plurality of encoded symbols, the SISO decoder comprising:

a top SISO that, based on a plurality of trellis metrics, calculates a first plurality of extrinsic values for each encoded symbol of the plurality of encoded symbols;
wherein the interleaver memory structure interleaves the first plurality of extrinsic values to generate a first “a priori probability” (app) information;
a bottom SISO that, based on the plurality of trellis metrics, calculates a second plurality of extrinsic values for each encoded symbol of the plurality of encoded symbols according to the respective rate control;
wherein the interleaver memory structure de-interleaves the second plurality of extrinsic values to generate a second “a priori probability” (app) information;
wherein the first “a priori probability” (app) information is fed back to the bottom SISO;
wherein the second “a priori probability” (app) information is fed back to the top SISO;
wherein the top SISO and the bottom SISO operate cooperatively to perform at least one iteration of iterative decoding to generate a plurality of soft symbol decisions, each soft symbol decision of the plurality of soft symbol decisions corresponds to an encoded symbol of the plurality of encoded symbols;
and
an output processor, communicatively coupled to the bottom SISO, that generates a hard symbol decision for each soft symbol decision of the plurality of soft symbol decisions thereby making a best estimate for each encoded symbol of the plurality of encoded symbols;
wherein the interleaver memory structure includes a first interleaver pattern memory, a second interleaver pattern memory, a first interleaver memory, and a second interleaver memory that are all implemented using single port memory structures;
during a first clock cycle:
a first interleaver pattern memory receives a first sequential read address;
a second interleaver pattern memory receives a first sequential write address;
during a second clock cycle:
the first interleaver pattern memory receives a second sequential write address;
the second interleaver pattern memory receives a second sequential read address;
a first read address is received from the first interleaver pattern memory for use by a first interleaver memory;
a first write address is received from the second interleaver pattern memory for use by a second interleaver memory;
during a third clock cycle:
the first interleaver pattern memory receives a third sequential read address;
the second interleaver pattern memory receives a third sequential write address;
a second write address is received from the first interleaver pattern memory for use by the first interleaver memory;
a second read address is received from the second interleaver pattern memory for use by the second interleaver memory;
a first data is read from the first interleaver memory;
a second data is written to the second interleaver memory;
and
wherein each of the first interleaver pattern memory, the second interleaver pattern memory, the first interleaver memory, and the second interleaver memory are implemented using single port memory structures.

24 more elements

An interleaver memory processing method, the method comprising:

during a first clock cycle:
providing a first sequential read address to a first interleaver pattern memory;
providing a first sequential write address to a second interleaver pattern memory;
during a second clock cycle:
providing a second sequential write address to the first interleaver pattern memory;
providing a second sequential read address to the second interleaver pattern memory;
receiving a first read address from the first interleaver pattern memory for use by a first interleaver memory;
receiving a first write address from the second interleaver pattern memory for use by a second interleaver memory;
during a third clock cycle:
providing a third sequential read address to the first interleaver pattern memory;
providing a third sequential write address to the second interleaver pattern memory;
receiving a second write address from the first interleaver pattern memory for use by the first interleaver memory;
receiving a second read address from the second interleaver pattern memory for use by the second interleaver memory;
reading a first data from the first interleaver memory;
and
writing a second data to the second interleaver memory.

13 more elements

Dependencies are inferred from the claim text.

Interleaver for iterative decoder

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Interleaver for iterative decoder

Life of this patent

Abstract

Claims47