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AssigneeSandbridge Technologies, Inc.
InventorsErdem Hokenek, C. John Glossner, Arthur Joseph Hoane, Mayan Moudgill, Shenghong Wang
Estimating the term…
A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing a thread-based eviction process that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array having multiple sets of memory locations, and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations. The directory has multiple entries each storing multiple ones of the tags, such that if there are n sets of memory locations in the memory array, there are n tags associated with each directory entry. The directory is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array. An entry in a particular one of the memory locations is selected for eviction from the given thread cache in conjunction with a cache miss event, based at least in part on at least a portion of a thread identifier of the given thread cache.
A cache memory for use in a multithreaded processor, the cache memory comprising a plurality of thread caches, at least a given one of the thread caches comprising:
A multithreaded processor comprising:
A method of controlling a cache memory in a multithreaded processor, the cache memory comprising a plurality of thread caches, at least a given one of the thread caches comprising a memory array having a plurality of sets of memory locations and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations, the directory having a plurality of entries each storing multiple ones of the tags, the method comprising the steps of:
Dependencies are inferred from the claim text.