Carry foreknowledge adder

A carry foreknowledge adder comprising:

• an adding circuit which adds binary numbers A and B of n bits;
• and
• a plurality of carry foreknowledge circuit blocks (j (j=0, 1, . . . , k−1)) that respectively corresponding to divisional portions Am−1, Am−2, . . . , A0 and Bm−1, Bm−2, . . . , B0 obtained by dividing said A and said B into integer K (K≧2) portions through setting m bits (2≦m<n) into a unit length, said carry foreknowledge circuit block preliminarily arithmetically operating each carry Ci (i=0, 1, . . . , m−1) corresponding to each of bit Ai and bit Bi and outputting them to said adding circuit, wherein
• said carry foreknowledge circuit block (j) has a plurality of arithmetic operating portions (j, i) in correspondence to each bit, that respectively arithmetically operate said carry Ci and output said carry Ci to said adding circuit;
• each upper said arithmetic operating portion (j, i) respectively corresponding to each of the bits of at least two digits from the most significant bit, in order to execute said arithmetical operation, has a logic circuit portion which receives a lower output signal outputted from a logic circuit portion arranged on an output terminal side of a lower said arithmetic operating portion (j, i) corresponding to the lower bit following under said at least two digits, and which is arranged on the output terminal side, and executes the arithmetic operation of said carry Ci by using said received lower output signal.