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US 2003/0225804 A1Published application
Average code generation circuit
AssigneeSun Microsystems, Inc.
InventorsCong Q. Khieu, Louise Gu
Life of this patent
Estimating the term…
Abstract
Disclosed is a method and circuit for generating an average binary code from at least two input binary codes. The circuit may be employed in an integrated circuit having first and second circuits for generating binary codes am−1:0 and bm−1:0, respectively. In one embodiment, the circuit asynchronously generates a binary code cm−1:0 representing an average of the binary codes am−1:0 and bm−1:0 generated by the first and second circuits, respectively.
Claims11
A method comprising:
- first and second circuits generating binary codes am−1:0 and bm−1:0, respectively;
- an asynchronous circuit generating binary code cm−1:0 in response to the asynchronous circuit receiving binary codes am−1:0 and bm−1:0;
- wherein if binary codes am−1:0 and bm−1:0 are identical to each other or if binary codes am−1:0 and bm−1:0 differ from each other by only one bit, the asynchronous circuit generates binary code cm−1:0 identical to one of the binary codes am−1:0 and bm−1:0;
- wherein if binary codes am−1:0 and bm−1:0 differ from each other by only two bits, the asynchronous circuit generates binary code cm−1:0 which is identical to a result of left shifting one of the binary codes am−1:0 and bm−1:0 by one bit with logical zero fill at the least significant bit thereof;
- wherein if binary codes am−1:0 and bm−1:0 differ from each other by three, four or five bits, the asynchronous circuit generates binary code cm−1:0 which is identical to a result of left shifting one of the binary codes am−1:0 and bm−1:0 by two bits with logical zero fill at the least significant bit thereof.
2 more elements
An integrated circuit comprising:
- first and second circuits for generating binary codes am−1:0 and bm−1:0, respectively;
- an asynchronous circuit coupled to the first and second circuits, wherein the asynchronous circuit is configured to generate a binary code cm−1:0 representing an average of the binary codes am−1:0 and bm−1:0 generated by the first and second circuits, respectively.
An integrated circuit comprising:
- first and second circuits for generating binary codes am−1:0 and bm−1:0, respectively;
- an asynchronous circuit for generating binary code cm−1:0 in response to the asynchronous circuit receiving binary codes am−1:0 and bm−1:0;
- wherein if binary codes am−1:0 and bm−1:0 are identical to each other or if binary codes am−1:0 and bm−1:0 differ from each other by only one bit, the asynchronous circuit generates binary code cm−1:0 identical to one of the binary codes am−1:0 and bm−1:0;
- wherein if binary codes am−1:0 and bm−1:0 differ from each other by only two bits, the asynchronous circuit generates binary code cm−1:0 which is identical to a result of left shifting one of the binary codes am−1:0 and bm−1:0 by one bit with logical zero fill at the least significant bit thereof;
- wherein if binary codes am−1:0 and bm−1:0 differ from each other by three, four or five bits, the asynchronous circuit generates binary code cm−1:0 which is identical to a result of left shifting one of the binary codes am−1:0 and bm−1:0 by two bits with logical zero fill at the least significant bit thereof.
2 more elements
Dependencies are inferred from the claim text.