Enable generator EG, and method of mapping data using the EG

Abstract

The invention discloses a cyclic generator of enabling/disabling signals (EG) adapted to convert an incoming data stream having a bit rate RI into an outgoing data stream having a bit rate R2, wherein R1≅mR2/n , m<n, m and n—integers being parameters of said EG selected to provide m enable signals per n clocks of the bit rate R2, wherein the EG is characterized by having a number of internal states <n and being capable of generating periodic enabling/disabling output signals such that the disable signals are optimally distributed among the enable signals. Also, there is disclosed a method of low-jitter mapping of the incoming data stream having a bit rate R1, into a succession of data frames of an outgoing data stream having a higher bit rate, wherein each of the frames comprises an overhead portion and a payload portion; the method comprises using the cyclic generator of enable/disable signals (EG) to control filling the payload portion of each data frame of the outgoing data stream with information bits of the incoming data stream diluted with stuffing bits, wherein the filling is performed at the bit rate R2, R1≅mR2/n, m<n, m and n are integers. The method comprises using at least one predetermined location in the overhead portion of at least one of the data frames to indicate an internal state of the EG corresponding to a suitable payload portion, for further de-mapping of that portion.

Dependencies are inferred from the claim text.