Method and system for deterministic control of an emulation

A system that deterministically evaluates operations of a circuit design comprising:

• an application module that determines a set of commands for execution by a design under test (DUT);
• a channel controller that delivers the set of commands to the DUT;
• and
• an event dispatcher that receives a set of events from the DUT that includes results of the execution of the set of commands.

A system that deterministically evaluates operations of a circuit design comprising:

• an application module that defines commands and test vectors for execution by a design under test (DUT);
• a channel controller that delivers the commands and the test vectors to the DUT;
• a source level debugger that monitors the DUT during the execution of the commands;
• an event dispatcher that receives events from the DUT, wherein the events includes results of the execution of the commands.

A method for deterministically evaluating operations of a circuit design comprising:

• determining a first set of commands for execution by a design under test (DUT);
• delivering the first set of commands to the DUT;
• monitoring the DUT during the execution of the first set of commands;
• receiving a first set of events from the DUT wherein the first set of events includes results of the execution of the first set of commands;
• and
• determining, from the first set of events, a second set of commands for execution by the DUT, wherein the second set of commands tests one or more operations performed by the DUT.

A method for simulating events in an emulation-based environment comprising:

• configuring verification commands for a design under test (DUT);
• forwarding the verification commands to the DUT through a plurality of transactors;
• receiving response messages from the DUT;
• processing the response messages from the DUT;
• and
• forwarding the response messages to the transactors.

A method for deterministically evaluating operations of a circuit design comprising:

• determining a first set of commands for execution by the circuit design;
• delivering the first set of commands to the circuit design;
• monitoring the circuit design during the execution of the first set of commands;
• receiving a first set of events from the circuit design wherein the first set of events includes results of the execution of the first set of commands;
• and
• determining, from the first set of events, a second set of commands for execution by the circuit design, wherein the second set of commands tests one or more operations performed by the circuit design.