A process for generating scrambling codes for CDMA communications, said codes being organized in primary scrambling codes (PSCs) and secondary scrambling codes (SSCs) having an I branch and a Q branch, characterized in that, to generate the primary scrambling code of order N, where N is between 0 and Nmax, and the secondary scrambling code of order K, where K is between 1 and Kmax, within the set identified by the primary scrambling code of order N, it comprises the operations of:
- a) generating a first m-sequence using a T-bit Fibonacci linear feedback shift register (LFSR), designated as X, corresponding to a first polynomial (X(D)) over the Galois field (GF(2)) and initialized with a first T-bit initialization word of rank N (XN-INIT), corresponding to the primary scrambling code of order N;
- b) generating a second m-sequence using a Fibonacci linear feedback shift register (LFSR), designated as Y, corresponding to a second polynomial (Y(D)) over the Galois field (GF(2)) and initialized with a second T-bit initialization word of rank 0 (Y0-INIT);
- c) modulo-2 adding said first sequence and said second sequence so as to form the I branch of said primary scrambling code;
- d) generating a first T-bit masking word of rank 0 (X0-MASK) corresponding to the polynomial time shift (X0(D)) and modulo-2 adding the intermediate taps of said register X chosen using said first masking word (X0-MASK), so as to generate a third sequence;
- e) generating a second T-bit masking word of rank 0 (Y0-MASK) corresponding to the polynomial time shift (Y0(D)) and modulo-2 adding the intermediate taps of said register Y chosen using said second masking word (Y0-MASK), so as to generate a fourth sequence;
- f) modulo-2 adding said third sequence and said fourth sequence so as to form the Q branch of said primary scrambling code;
- g) starting from the least significant Kmax bits of said register X, choosing the K-th intermediate tap corresponding to the secondary scrambling code of order K within said set, so as to generate a fifth sequence;
- h) modulo-2 adding said second sequence and said fifth sequence so as to form the I branch of said secondary scrambling code;
- i) modulo-2 adding the intermediate taps of said register X masked by means of said first masking word of rank N (XN-MASK), so as to generate a sixth sequence;
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- j) modulo-2 adding said fourth sequence and said sixth sequence so as to form the Q branch of said secondary scrambling code.