Integrated circuit reset circuitry
AssigneeMicron Technology, Inc.
InventorFrankie Fariborz Roohparvar
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes a reset connection to reset the device in response to an externally provided signal. The reset connection is used during test operations to receive elevated supply voltages. The reset connection is coupled to a bias circuit to maintain an inactive state such that the integrated circuit is not reset during the test operation when the reset connection is not actively driven by the external supply.
Claims16
A memory device comprising:
- control circuitry to place the memory device in a test mode;
- a reset connection to receive an externally provided active low reset signal to reset the memory device, the reset connection can receive an elevated voltage during the test mode;
- an input buffer circuit coupled to the reset connection;
- and
- a pull-up bias circuit coupled to the reset connection, wherein the pull-up bias circuit is active only during the test mode.
A synchronous non-volatile memory device comprising:
- an array of non-volatile memory cells;
- control circuitry to place the memory device in a test mode in response to an external test command;
- a supply connection to receive a voltage supply, Vcc;
- a reset connection to receive an externally provided active low reset signal to reset the memory device, the reset connection can receive an elevated voltage during the test mode, where the elevated voltage is greater than Vcc;
- an input buffer circuit coupled to the reset connection;
- and
- a pull-up bias circuit coupled to the reset connection, wherein the pull-up bias circuit is active only during the test mode.
A method of operating a memory device comprising:
- initiating a test operation of the memory device;
- and
- activating a bias circuit coupled to a reset connection of the memory device during the test operation.
A method of operating a non-volatile memory device comprising:
- activating a pull-up bias circuit coupled to a reset connection of the memory device;
- coupling active low reset signals to the reset connection during a test operation using a first tester;
- disconnecting the first tester from the reset connection;
- and
- coupling an elevated supply voltage to the reset connection.
A method of operating a non-volatile memory device comprising:
- initiating a test operation of the memory device via externally provided commands;
- activating an internal pull-up bias circuit coupled to a reset connection of the memory device;
- coupling active low reset signals to the reset connection during a test operation using a first tester;
- disconnecting the first tester from the reset connection such that the reset connection is not actively driven from an outside source, wherein the activated pull-up bias circuit prohibits a voltage on the reset connection from transitioning to a low state;
- and
- coupling an elevated supply voltage to the reset connection during the test operation, wherein the elevated voltage supply is greater than a memory voltage supply, Vcc.
A synchronous non-volatile memory device comprising:
- an array of non-volatile memory cells;
- control circuitry to place the memory device in a test mode in response to an external test command;
- a supply connection to receive a voltage supply, Vcc;
- a reset connection to receive an externally provided active low reset signal to reset the memory device;
- an input buffer circuit coupled to the reset connection;
- and
- a pull-up circuit coupled to the reset connection, wherein the pull-up circuit is active only during the test mode, the pull-up circuit comprises,
- a current limiting resistor coupled to the reset connection, and
- a transistor coupled between the resistor and Vcc.
Dependencies are inferred from the claim text.