Synchronous type semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsKazuaki Kawaguchi, Shigeo Ohshima, Nobuo Watanabe, Yoshinori Ogawa
Life of this patent
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Abstract
A synchronous type semiconductor device which inputs/outputs data with respect to a host includes a memory circuit, command decoder and CAS latency setting circuit. The command decoder decodes a command control signal input from the host in synchronism with a clock input from the host and outputs the decoded command to the memory circuit. The command includes a read command and mode register set command. The CAS latency setting circuit sets CAS latency in a read cycle based on a predetermined command output from the command decoder and a function control signal input from the host. The predetermined command is a command other than the mode register set command.
Claims19
A synchronous type semiconductor device which inputs/outputs data with respect to a host comprising:
- a memory circuit;
- a command decoder which decodes a command control signal input from the host in synchronism with a clock input from the host and outputs the decoded command to the memory circuit, the command including a read command and mode register set command;
- and
- a CAS latency setting circuit which sets CAS latency in a read cycle based on a predetermined command output from the command decoder and a function control signal input from the host, the predetermined command being a command other than the mode register set command.
A synchronous type semiconductor device which inputs/outputs data with respect to a host comprising:
- a clock frequency detecting circuit which detects a frequency of a clock input from the host;
- and
- a CAS latency setting circuit which sets CAS latency based on the clock frequency detected by the clock frequency detecting circuit.
A synchronous type semiconductor device which inputs/outputs data with respect to a host comprising:
- a clock phase control circuit which controls timing of a clock input from the host and an internal clock of the synchronous type semiconductor device and includes a forward pulse delay line and backward pulse delay line, the forward pulse delay line and backward pulse delay line each of which includes a plurality of delay circuits with the same configuration, the delay circuits being connected in series;
- and
- a CAS latency setting circuit which sets CAS latency based on delay output signals output from predetermined delay circuits in the delay circuits which one of the forward pulse delay line and backward pulse delay line includes.
Dependencies are inferred from the claim text.