Redundancy circuit and method for semiconductor memory devices
AssigneeSTMicroelectronics S.r.l.
InventorDavid C. McClure
Life of this patent
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Abstract
A redundancy circuit and method are disclosed for replacing at least one defective memory cell in a memory device. The redundancy circuit may include redundant decode circuitry for selectively maintaining an address of a defective memory cell in the memory device, receiving the input address and generating an output signal having a value indicative of whether the input address corresponds to the address of the defective memory cell. The redundancy circuit may further include a plurality of redundant storage circuits for selectively maintaining data values, and redundant control circuitry for selectively and individually accessing a first of the redundant storage circuits based upon the value of the output signal of the redundant decode circuitry.
Claims33
A memory device, comprising:
- an array of memory cells, each memory cell being capable of maintaining a data value therein;
- address decode circuitry for receiving an input address and selecting at least one memory cell based upon the value of the input address;
- redundant decode circuitry for selectively maintaining an address of a defective memory cell in the array, receiving the input address and generating an output signal having a value indicative of whether the input address corresponds to the address of the defective memory cell;
- a plurality of redundant storage circuits for selectively maintaining data values;
- and
- redundant control circuitry for selectively and individually accessing a first of the redundant storage circuits based upon the value of the output signal of the redundant decode circuitry.
A method of performing a memory access operation in a memory device having an array of memory cells and at least one storage circuit, comprising:
- receiving an input address signal;
- comparing the input address signal with an address of a defective memory cell in the memory device;
- and
- upon an affirmative determination that the input address signal corresponds to the address of the defective memory cell, individually accessing the storage circuit, the step of accessing occurring with substantially the same timing as the timing associated with accessing a memory cell in the array.
A computing apparatus, comprising:
- a processing element;
- and
- a memory device coupled to the processing element for storing information, comprising:
- a plurality of memory cells, the memory cells including a defective memory cell;
- decode circuitry for receiving an address input provided to the memory device and selecting at least one memory cell based upon the address input received;
- a storage circuit capable of maintaining a data value;
- redundant detection circuitry for comparing the address input with an address of the defective memory cell;
- an external data port;
- and
- circuitry coupled to the storage circuit for selectively and individually accessing the storage circuit based upon the comparison.
A memory device, comprising:
- a plurality of memory cells, the memory cells including a defective memory cell;
- decode circuitry for receiving an address input provided to the memory device and selecting at least one memory cell based upon the address input received;
- a storage circuit capable of maintaining a data value;
- redundant detection circuitry for comparing the address input with an address of the defective memory cell;
- an external data port;
- and
- circuitry coupled to the storage circuit for selectively and individually accessing the storage circuit based upon the comparison.
A memory device, comprising:
- a plurality of memory cells, the memory cells including a defective memory cell;
- decode circuitry for receiving an address input provided to the memory device and selecting at least one memory cell;
- a storage circuit, separate from the memory cells, capable of maintaining a data value;
- redundant detection circuitry for comparing the address input with an address of the defective memory cell;
- an external data port;
- and
- means, coupled to the storage circuit, for selectively and individually replacing, during the course of a memory access operation, the defective memory cell with the storage circuit based upon the comparison.
Dependencies are inferred from the claim text.