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AssigneeSamsung Electronics Co., Ltd.
InventorsDae-Seok Byeon, Kyeong-Han Lee
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Embodiments of the invention provide a power-on reset function that establishes logic circuits in a memory chip at an initial stable state and a power-on read function that triggers a read operation of the memory chip. A first voltage detector output signal transitions when a power supply voltage reaches a first voltage, setting the logic circuits at the initial stable state. A second voltage detector output signal transitions when the power supply voltage reaches a second voltage, placing a latch in a set state that results in activation of a power-on read signal. A power-on read operation is carried out according to the activation of the power-on read signal. If the power supply voltage is not lowered below the first voltage, the second voltage detector output signal does not transition. Accordingly, embodiments are capable of preventing power-on read operations that are unnecessarily performed owing to power noise.
A power detecting circuit which initializes logic circuits in a flash memory chip at power-on and commences a stable read operation of the flash memory device, comprising:
A power detecting circuit which initializes logic circuits in a flash memory chip at power-on and allows for a read operation of the memory device, comprising:
A flash memory device comprising:
A voltage level detecting circuit in a memory device, the voltage level detecting circuit comprising:
A method of generating a power-on reset signal, by which logic circuits in a flash memory device are reset, and a power-on read signal, by which a read operation of the memory device is triggered, comprising:
A method of reading a memory device at power-on, comprising:
A method of generating a power on reset signal, comprising:
Dependencies are inferred from the claim text.