Ferroelectric memory transistor

A method of forming a ferroelectric memory transistor comprising:

• preparing a substrate, including forming active regions and an oxide device isolation region;
• depositing a gate oxide layer;
• depositing a gate placeholder layer;
• masking and removing a portion of the gate placeholder layer and the gate oxide layer to form a gate placeholder structure in a gate region;
• depositing a layer of oxide over the structure to a depth of approximately twice that of the gate placeholder layer;
• smoothing the structure to the level of the gate placeholder layer;
• removing the gate placeholder structure and the gate oxide layer in the gate region, forming a gate void in the gate region;
• depositing a high-k insulator layer over the structure and in the gate void to from a high-k cup;
• filling the high-k cup with a ferroelectric material to form a ferroelectric element;
• smoothing the structure to the upper level of the ferroelectric element;
• depositing a high-k upper insulator layer and removing excess high-k material to form a high-k cap over the ferroelectric element;
• depositing a top electrode over the high-k cap to form a gate electrode and gate stack;
• depositing a layer of passivation oxide over the structure;
• etching the passivation oxide to from contact vias to the active regions and the gate gate stack;
• and
• metallizing the structure to complete the ferroelectric memory transistor.

A method of forming a ferroelectric memory transistor comprising:

• preparing a substrate, including forming active regions and an oxide device isolation region;
• depositing a gate oxide layer;
• depositing a gate placeholder layer to a thickness of between about 98 nm to 598 mn;
• masking and removing a portion of the gate placeholder layer and the gate oxide layer to form a gate placeholder structure in a gate region;
• depositing a layer of oxide over the structure to a depth of approximately twice that of the gate placeholder layer;
• smoothing the structure to the level of the gate placeholder layer;
• removing the gate placeholder structure and the gate oxide layer in the gate region, forming a gate void in the gate region;
• depositing a high-k insulator layer over the structure and in the gate void to from a high-k cup having a thickness of between about 2 nm to 10 nm;
• filling the high-k cup with a ferroelectric material to form a ferroelectric element;
• smoothing the structure to the upper level of the ferroelectric element;
• depositing a high-k upper insulator layer and removing excess high-k material to form a high-k cap having a thickness of between about 2 nm to 10 nm over the ferroelectric element;
• depositing a top electrode over the high-k cap to form a gate electrode and gate stack;
• depositing a layer of passivation oxide over the structure;
• etching the passivation oxide to from contact vias to the active regions and the gate stack;
• and
• metallizing the structure to complete the ferroelectric memory transistor.