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AssigneesHitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
InventorsYoshio Takazawa, Toshio Yamada, Kazumasa Yanagisawa, Takashi Hayasaka
Estimating the term…
There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.
A semiconductor integrated circuit comprising a plurality of memories of different access data widths and logical circuits which can control access to said memories, wherein a common test bus connected to a plurality of said memories and a plurality of bridge circuits which converts the test data information from said common test bus to the inherent access data width of each memory and then supplies said data to the corresponding memory are provided in order to enable the parallel tests by supplying the test data information in parallel to a plurality of said memories from the common test bus.
A semiconductor integrated circuit comprising a plurality of memories of different address decode logics and logical circuits for controlling access to said memories, wherein a common test bus connected to a plurality of said memories and a plurality of bridge circuits which convert the test address information from said common test bus to the inherent bit format of each memory and then supplies said data to the corresponding memory are provided in order to enable the parallel tests by supplying in parallel the test address information to a plurality of memories from the common test bus.
A semiconductor integrated circuit comprising a plurality of memories of different access data widths and logical circuits which can control access to said memories, wherein a common test bus connected to a plurality of said memories and a plurality of bridge circuits which converts the test data information from said common test bus to the inherent access data width of each memory and supplies these data to the corresponding memory and moreover converts the test address information from said common test bus to the inherent bit format of each memory and then supplies these data to the corresponding memory are provided in order to enable the parallel tests by supplying in parallel the test data information and test address information to a plurality of said memories from the common test bus.
A testing method for testing in parallel a plurality of memories of different access data widths via the common test bus, comprising the steps of:
A testing method for testing in parallel a plurality of memories of different address decode logics via the common test bus, comprising the steps of:
Dependencies are inferred from the claim text.