Method for designing semiconductor circuit

A method for designing a semiconductor circuit, comprising:

• a macro design step for securing beforehand internal wiring prohibiting regions which enable to wire external wiring vertically and horizontally across the macro, and buffer allocable regions which allocate buffers as repeaters for the external wirings, and for designing plural macros in which plural cells are connected;
• a macro timing analysis step for analyzing timing of the macro designed in said macro design step;
• a whole circuit design step for configuring the plural macros and designing the external wirings;
• a whole circuit timing analysis step for analyzing timing of the whole circuit designed in said whole circuit design step;
• and
• a whole circuit modification step for wiring the external wirings across the macro by passing through the internal wiring prohibiting regions of the macros, and for configuring the buffers as repeaters which are connected with the external wirings inside the buffer allocable regions of the macros, when an error is found in the timing analysis of the whole circuit.