Architecture and design of universal IC test system

A universal test system for testing an IC device under test (DUT), comprising:

• a host computer for controlling an overall operation of the universal test system;
• interface software for interfacing the host computer and the universal test system, the interface software including graphic user interface (GUI) establishing an input means, command control and viewer for monitoring and editing test vectors for the universal test system;
• data interpretation and management software for interpreting and managing data from the host computer through the interface software;
• and
• universal test system hardware having an event tester mode for testing DUT by test vectors produced based on event data derived directly from simulation of design data of DUT produced in an EDA (electronic design automation) environment and a cyclized tester mode for testing DUT by test vectors produced based on test data formulated in a cyclized format in which each test vector is defined by waveform, a test rate, and a timing with respect to the test rate.