Cyclic redundancy check circuit for use with self-synchronous scramblers

A circuit for detecting and correcting errors in a bit stream, said circuit comprising:

• a plurality of bit circuit elements coupled to receive and store said bit stream, each bit circuit element corresponding to a specific bit in a bit pattern;
• at least one operation circuit element for performing operations between the contents of at least two of said bit circuit elements;
• and
• at least two logic gates for determining if the contents of said bit circuit elements match specific bit patterns, at least one of said at least two logic gate receiving inputs from said bit circuit elements;
• wherein an output of said circuit causes a state of at least one bit in said bit stream to change if contents of said bit circuit elements match at least one of said plurality of specific bit patterns;
• and
• wherein said bit patterns correspond to errors that have occurred in the transmitted data.

A circuit for detecting errors in a bit stream, the circuit comprising:

• operation means for performing bitwise operations between at least a portion of said bit stream and a bit pattern derived from said bit stream;
• and
• detection means for detecting if a bitwise operation between at least a portion of said bit stream and said bit pattern derived from said bit stream produces a result indicating at least one error in said bit stream;
• wherein said operation means implements a bitwise operation corresponding to
• B(x)=Rem(D(x)/G(x)
• where
• D(x) is said at least a first portion of said bit stream;
• G(x) is said bit pattern derived from said bit stream;
• and
• B(x) is a remainder of a division operation between D(x) and G(x);
• such that said detection means detects when B(x) does not equal 0.