Error detection in dynamic logic circuits
AssigneeFujitsu Limited
InventorsPranjal Srivastava, Ajay Naini, Atul Dhablania
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Abstract
Error detection apparatus and methods for dynamic logic are provided. Circuit errors are detected by comparing true and complement signals to ensure they are in fact complementary signals. A pseudocomplement technique is used to implement an adder in which distinct logic cones generate the true and complement carry signals. Other embodiments comprising additional features, such as shared logic cone decomposition, are also provided.
Claims27
A method for detecting errors in a domino logic circuit, the method comprising:
- obtaining a true signal in a first logic cone;
- obtaining a complement of the true signal in a second logic cone;
- comparing the true signal and the complement of the true signal to determine whether the true signal and the complement of the true signal are logical complements;
- and
- generating an error signal responsive to the comparing of the true signal and the complement of the true signal.
An apparatus for detecting errors in a domino logic circuit, the apparatus comprising:
- a first logic cone configured to produce a true signal;
- a second logic cone configured to produce a complement of the true signal;
- and
- a comparator configured to determine whether the true signal and the complement of the true signal are logical complements, the comparator further configured to produce an error signal.
An apparatus for detecting errors in a domino logic circuit, the apparatus comprising:
- means for producing a true signal in a first logic cone;
- means for producing a complement of the true signal in a second logic cone;
- means for comparing the true signal and the complement of the true signal to determine whether the true signal and the complement of the true signal are logical complements;
- and
- means for generating an error signal responsive to a comparison performed by the means for comparing.
Dependencies are inferred from the claim text.