Method and apparatus for virtual register renaming to implement an out-of-order processor

A method for executing an instruction by a processor comprising the steps of:

• providing a logical register file having at least one specified logical register for storing an architected operand;
• providing a physical register file having at least one specified physical register for storing a speculative operand;
• providing a plurality of virtual register numbers, one of the plurality of virtual register numbers being a specified virtual register number, a number of the plurality of virtual register numbers being greater than the number of logical registers in the logical register file plus a number of physical registers in the physical register file, the specified physical register is directly indexed to the specified logical register;
• providing a register alias table that associates a logical register number for the specified logical register with the specified virtual register number;
• renaming the architected operand based on the specified virtual register number;
• comparing a set of bits of the specified virtual register number with a virtual register number broadcasted from a producer instruction in order to determine whether an operand produced by the producer instruction is an operand needed to execute the instruction;
• comparing check tag bits of the specified virtual register number with a speculative operand check tag to determine whether the producer instruction is a correct producer instruction or an incorrect producer instruction;
• executing the instruction based on the speculative operand if the comparing check tag bits step indicates that the producer instruction is the correct producer instruction;
• executing the instruction based on the architected operand if the comparing check tag bits indicates that the producer instruction is the incorrect producer instruction;
• and
• storing data generated by executing the instruction at a destination physical register.

A computing device comprising:

• a logical register file means for storing an architected state of an architected operand;
• a physical register file means for storing a speculative state of a speculative operand;
• a virtual register number means for mapping the logical register means to the physical register means;
• and
• a processor means for performing out-of-order processing of an instruction set based on the architected operand or the speculative operand.