Interface for devices having different data bus widths and data transfer method using the interface

An interface interfacing a plurality of first data buses each having an N-bit data width and a second data bus having a 2N-bit data width, the interface comprising:

• a first selection circuit outputting the data on a data bus selected from the first data buses in response to a first selection signal;
• a first conversion circuit pre-fetching first and second N-bit data on the selected data bus in response to read control signals and transferring 2N-bit data comprised of the pre-fetched first and second N-bit data to the second data bus;
• and
• a second conversion circuit converting the 2N-bit data on the second data bus into N-bit data in response to write control signals and transferring the N-bit data to a data bus selected from the first data buses.

An interface comprising:

• a first data bus having an N-bit data width;
• a second data bus having an N-bit data width;
• a first selection circuit selecting the data on the first data bus or the data on the second data bus in response to a first selection signal;
• a first conversion circuit pre-fetching the output signals of the selection circuit in response to read control signals and transferring 2N-bit data comprised of the pre-fetched data to a third data bus having a 2N-bit data width;
• and
• a second conversion circuit dividing 2N-bit data on the third data bus by N-bit data in response to write control signals and transferring the divided N-bit data to either the first data bus or the second data bus.

A method of transferring the data on a first data bus of an M-bit data width to a second data bus of an N-bit data width or a third data bus of an N-bit data width, the method comprising:

• latching the M-bit data on the first data bus in response to a first write control signal;
• dividing the latched M-bit data latched by N bits, latching each of the divided N-bit data in response to a second write control signal and selectively outputting the latched N-bit data in response to a selection signal;
• and
• transferring the output latched N-bit data to the first or second data bus in response to a control signal.

A computer system, comprising:

• an M-bit system bus;
• N-bit peripheral buses;
• and
• an interface interfacing the M-bit system bus and the N-bit peripheral buses without using a first-in-first-out memory.

A computer system, comprising:

• an M-bit system bus;
• N-bit peripheral buses;
• and
• an interface interfacing the M-bit system bus and the N-bit peripheral buses using direct memory access control signals.