Load-linked/store conditional mechanism in a CC-NUMA system
AssigneeBroadcom Corporation
InventorJoseph B. Rowlands
Life of this patent
Estimating the term…
Abstract
A node includes a processor coupled to an interconnect and a memory bridge coupled to the interconnect. The processor is configured to maintain a first indication of whether or not a modification of data at a first address has been detected by the processor after a most recent load-linked (LL) instruction was executed by the processor to the first address. The memory bridge is responsible for internode coherency within the node, and is configured to initiate a first transaction on the interconnect in response to receiving a probe command from another node. The processor is configured, during a time period in which the processor has a second transaction outstanding to the first address, to change the first indication to the first state responsive to the first transaction.
Claims19
A node comprising:
- a processor coupled to an interconnect, wherein the processor is configured to maintain a first indication of whether or not a modification of data at a first address has been detected by the processor after a most recent load-linked (LL) instruction was executed by the processor to the first address, and wherein the first indication being in a first state that indicates that the modification has been detected prevents a store conditional (SC) instruction executed on the processor from completing successfully;
- and
- a memory bridge coupled to the interconnect, wherein the memory bridge is responsible for internode coherency within the node, and wherein the memory bridge is configured to initiate a first transaction on the interconnect in response to receiving a probe command from another node;
- wherein the processor is configured, during a time period in which the processor has a second transaction outstanding to the first address, to change the first indication to the first state responsive to the first transaction.
A processor comprising:
- a storage location configured to store a first address and a first indication corresponding to the first address, wherein the first indication is indicative of whether or not a modification of data at the first address has been detected by the processor after a most recent load-linked (LL) instruction was executed by the processor to the first address, and wherein the first indication being in a first state that indicates that the modification has been detected prevents a store conditional (SC) instruction executed on the processor from completing successfully;
- and
- a control circuit coupled to receive transactions from an interconnect to which the processor is coupled during use, wherein the control circuit is configured to distinguish between a first transaction initiated in response to a probe command from a different node than the node including the processor and a second transaction initiated by an agent within the node to modify the data at the first address, and wherein the control circuit is configured, during a time period in which the processor has a third transaction outstanding to the first address, to cause the processor to change the first indication to the first state responsive to the first transaction but not to change the first indication responsive to the second transaction.
A method comprising:
- in a processor in a first node, detecting a first transaction corresponding to a probe command received from a second node during a time period that a second transaction is outstanding from the processor to a first address, the processor maintaining a first indication indicative of whether or not a modification of data at a first address has been detected by the processor after a most recent load-linked (LL) instruction was executed by the processor to the first address, and wherein the first indication being in a first state that indicates that the modification has been detected prevents a store conditional (SC) instruction executed on the processor from completing successfully;
- changing the first indication to the first state during the time period responsive to the detecting.
Dependencies are inferred from the claim text.