US 2003/0216013 A1 · Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicone structures

Abstract

A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.

Claims32

Dependent claims

A method of modulating grain size in a polysilicon layer comprising:

forming said layer of polysilicon on a substrate;
and
performing an ion implantation of a polysilicon grain size modulating species into said polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.

Dependencies are inferred from the claim text.

Facts

Application

10/147,270Filed 15 May 2002

Published

20 Nov 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification21 codes

H10P 30/204
Characterised by the semiconductor materials: into Group IV semiconductors
H10D 10/021
Manufacture or treatment: of heterojunction BJTs [HBT]
H10D 10/861
Vertical heterojunction BJTs: having an emitter region comprising one or more non-monocrystalline elements of Group IV, e.g. amorphous silicon
H10D 10/891
Vertical heterojunction BJTs: comprising lattice-mismatched active layers, e.g. SiGe strained-layer transistors

Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicone structures

Life of this patent

Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicone structures

Life of this patent

Abstract

Claims32