Refresh control circuit and method for semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorJin Hee Cho
Life of this patent
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Abstract
A refresh control circuit and a method for refreshing control of a semiconductor memory device are described. The refresh control circuit includes a sense amplifier control circuit configured to generate a sense amplifier driving signal by selectively applying a first delay time and a second delay time (first delay time+third delay time) in response to a sense amplifier enable signal and a refresh command signal (or refresh fail detect signal), and a sense amplifier driver configured to output a sense amplifier driving voltage by applying the first delay time or the second delay time according to a mode.
Claims15
A refresh control circuit for a semiconductor memory device, the circuit comprising:
- a sense amplifier control circuit configured to generate a sense amplifier driving signal by selectively applying a first delay time and a second delay time in response to a sense amplifier enable signal and a refresh command signal, wherein the second delay time is a sum of the first delay time and a third delay time having a positive value;
- and
- a sense amplifier driver configured to output a sense amplifier driving voltage by applying the first delay time in a normal operation and the second delay time in a refresh operation.
A refresh control circuit for a semiconductor memory device, the circuit comprising
- a row address comparing unit configured to compare a row address having previously-recorded refresh failure with an internal row address, and to generate a refresh fail detect signal in response to a refresh command signal;
- and
- a sense amplifier control unit configured to output a sense amplifier driving voltage by applying a first delay time in a refresh operation for a general row address and a second delay time in a refresh operation for the row address having the previously-recorded refresh failure in response to the refresh fail detect signal and a sense amplifier enable signal, wherein the second delay time is a sum of the first delay time and a third delay time having a positive value.
A refresh control method for a semiconductor memory device, the method comprising:
- generating an internal row address for a refresh operation in response to a refresh command signal;
- generating a refresh fail detect signal by comparing a row address having previously-recorded failure with the internal row address in a refresh operation;
- and
- driving a sense amplifier by supplying an initial sense amplifier driving voltage for the row address having the previously-recorded refresh failure longer than for a general row address in response to the refresh fail detect signal in the refresh operation.
Dependencies are inferred from the claim text.