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US 2003/0214865 A1Published application
Semiconductor memory having multiple redundant columns with offset segmentation boundaries
AssigneeMicron Technology, Inc.
InventorGreg A. Blodgett
Life of this patent
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Abstract
A memory device with a segmented column architecture that allows for single bank repair across any two row blocks is disclosed. Multiple redundant columns are provided that have offset segment boundaries, i.e., a first redundant column is divided into four segments consisting of row block <0,1>, row block <2,3>, row block <4,5> and row block <6,7>, and a second redundant column is divided into four segments consisting of row block <1,2>, row block <3,4>, row block <5,6> and row block <0,7>. By offsetting the segment boundaries, the repair of the memory device can be optimized by repairing any two adjacent row blocks with only one column segment by selecting the appropriate redundant column segment.
Claims60
A memory device comprising:
- a first bank of memory cells arranged in rows and columns;
- a plurality of row lines for accessing memory cells in respective rows of said first bank based on a row address, said plurality of row lines being divided into a plurality of row blocks, each row block containing a respective plurality of row lines;
- a plurality of row decoders respectively coupled to said blocks of row lines for selectively activating an addressed row line;
- a plurality of column lines, each of said plurality of column lines being used to access memory cells in a respective column of said first bank;
- a column decoder coupled to said plurality of column lines for selectively activating an addressed column of said first bank;
- at least one first redundant column line for accessing memory cells in at least one first redundant column of said first bank, said at least one first redundant column being used to repair out defective memory cells in a column of said first bank, said at least one first redundant column being divided into a plurality of column segments, each of said column segments spanning at least two blocks of rows of said first bank of memory cells;
- at least one second redundant column line for accessing memory cells in at least one second redundant column of said first bank, said at least one second redundant column being used to repair out defective memory cells in a column of said first bank, said at least one second redundant column being divided into a plurality of column segments, each of said column segments spanning at least two blocks of rows of said first bank of memory cells, at least some of said segments of said at least one second redundant column having boundaries that are offset from boundaries of said segments of said at least one first redundant column;
- and
- a redundant column decoder coupled to said at least one first redundant column line and said at least one second redundant column line for selectively activating one of said at least one first redundant column and said at least one second redundant column when a repaired out column line is selected.
6 more elements
A memory device comprising:
- a first bank of memory cells arranged in rows and columns,
- at least one first redundant column line for accessing memory cells in at least one first redundant column of said first bank, said at least one first redundant column being used to repair out defective memory cells in a column of said first bank, said at least one first redundant column being divided into a plurality of column segments;
- and
- at least one second redundant column line for accessing memory cells in at least one second redundant column of said first bank, said at least one second redundant column being used to repair out defective memory cells in a column of said first bank, said at least one second redundant column being divided into a plurality of column segments, at least some of said segments of said at least one second redundant column being offset with respect to at least some of said segments of said at least one first redundant column;
- and
- a redundant column decoder coupled to said at least one first redundant column line and said at least one second redundant column line for selectively activating one of said at least one first redundant column and said at least one second redundant column when a repaired out column line is selected.
3 more elements
A memory device comprising:
- a first bank of memory cells arranged in rows and columns;
- and
- a first redundant column of said first bank, said first redundant column used to repair out defective memory cells in a column of said first bank, said first redundant column being divided into a plurality of column segments, said column segments having programmable boundaries.
A processor system comprising:
- a central processing unit;
- and
- a memory device connected to said processing unit to receive data from and supply data to said central processing unit, said memory device comprising:
- a first bank of memory cells arranged in rows and columns;
- a plurality of row lines for accessing memory cells in respective rows of said first bank based on a row address, said plurality of row lines being divided into a plurality of row blocks, each row block containing a respective plurality of row lines;
- a plurality of row decoders respectively coupled to said blocks of row lines for selectively activating an addressed row line;
- a plurality of column lines, each of said plurality of column lines being used to access memory cells in a respective column of said first bank;
- a column decoder coupled to said plurality of column lines for selectively activating an addressed column of said first bank;
- at least one first redundant column line for accessing memory cells in at least one first redundant column of said first bank, said at least one first redundant column being used to repair out defective memory cells in a column of said first bank, said at least one first redundant column being divided into a plurality of column segments, each of said column segments spanning at least two blocks of rows of said first bank of memory cells;
- at least one second redundant column line for accessing memory cells in at least one second redundant column of said first bank, said at least one second redundant column being used to repair out defective memory cells in a column of said first bank, said at least one second redundant column being divided into a plurality of column segments, each of said column segments spanning at least two blocks of rows of said first bank of memory cells, at least some of said segments of said at least one second redundant column having boundaries that are offset from boundaries of said segments of said at least one first redundant column;
- and
- a redundant column decoder coupled to said at least one first redundant column line and said at least one second redundant column line for selectively activating one of said at least one first redundant column and said at least one second redundant column when a repaired out column line is selected.
9 more elements
A processor system comprising:
- a central processing unit;
- and
- a memory device connected to said central processing unit to receive data from and supply data to said central processing unit, said memory device comprising:
- a first bank of memory cells arranged in rows and columns,
- at least one first redundant column line for accessing memory cells in at least one first redundant column of said first bank, said at least one first redundant column being used to repair out defective memory cells in a column of said first bank, said at least one first redundant column being divided into a plurality of column segments;
- and
- at least one second redundant column line for accessing memory cells in at least one second redundant column of said first bank, said at least one second redundant column being used to repair out defective memory cells in a column of said first bank, said at least one second redundant column being divided into a plurality of column segments, at least some of said segments of said at least one second redundant column being offset with respect to at least some of said segments of said at least one first redundant column;
- and
- a redundant column decoder coupled to said at least one first redundant column line and said at least one second redundant column line for selectively activating one of said at least one first redundant column and said at least one second redundant column when a repaired out column line is selected.
6 more elements
A processor system comprising:
- a central processing unit;
- and
- a memory device connected to said processing unit to receive data from and supply data to said central processing unit, said memory device comprising:
- a first bank of memory cells arranged in rows and columns;
- and
- a first redundant column of said first bank, said first redundant column used to repair out defective memory cells in a column of said first bank, said first redundant column being divided into a plurality of column segments, said column segments having programmable boundaries.
3 more elements
A method for repairing out at least one defective memory cell in a memory device, said method comprising:
- segmenting a first of a plurality of redundant columns into a plurality of segments such that each segment corresponds to at least two row blocks of said memory device;
- segmenting a second of said plurality of redundant columns into a plurality of segments such that each segment corresponds to at least two row blocks of said memory device, at least some of said segments of said second of said plurality of redundant columns being offset with respect to at least some of said segments of said first of said plurality of redundant columns;
- activating one of said first and second of said plurality of redundant columns;
- selecting one of said plurality of segments of said activated redundant column;
- and
- repairing out said at least one defective memory cell with said selected segment.
3 more elements
A method for repairing out a defective memory cell in a memory device, said method comprising:
- locating said defective memory cell in said memory device;
- identifying a sense amplifier connected to said defective memory cell;
- programming a segment of a redundant column such that said segment spans all memory cells connected to said identified sense amplifier;
- and
- repairing out said defective memory cell with said segment.
2 more elements
Dependencies are inferred from the claim text.