Reduced size multi-port register cell

A register cell, comprising:

• a storage element, having true and complement inputs;
• and
• N write circuits, each coupled to said storage element, each consisting essentially of:
• a first input wire, for transmitting a binary value to write into said storage element;
• a first transistor, coupling said first input wire to said true input;
• second and third transistors, coupled in series to said complement input, wherein said first input wire is also coupled to said third transistor to selectively turn on said third transistor to provide a complement of said binary value to said second transistor;
• and
• a second input wire, coupled to said first and second transistors, for selectively turning on said first and second transistors to selectively enable writing said binary value to said storage element.

A register cell, consisting essentially of:

• a storage element, having true and complement inputs;
• N write circuits, each coupled to said storage element, each comprising:
• a first input wire, for transmitting a binary value to write into said storage element;
• a first transistor, coupling said first input wire to said true input;
• second and third transistors, coupled in series to said complement input, wherein said first input wire is also coupled to said third transistor to selectively turn on said third transistor to provide a complement of said binary value to said second transistor;
• and
• a second input wire, coupled to said first and second transistors, for selectively turning on said first and second transistors to selectively enable writing said binary value to said storage element;
• and
• M read circuits, coupled to said storage element.

A register cell, comprising:

• a storage element, for storing a bit;
• N write ports, each comprising exactly two metal wires;
• and
• N write circuits, each coupling a corresponding one of said N write ports to said storage element, each comprising exactly three transistors.

A multi-ported register cell, comprising:

• a storage element, for storing a bit;
• N sets of only three transistors, each of said N sets of only three transistors coupled to said storage element, for writing said bit into said storage element;
• and
• N sets of only two metal wires, each of said N sets of only two metal wires coupled to a corresponding one of said N sets of only three transistors, for writing said bit into said storage element.