Computer systems, processes for forming a SRAM cell, processes for turning a SRAM cell off, processes for writing a SRAM cell and processes for reading data from a SRAM cell

A two-transistor SRAM cell comprising:

• a first FET being an ultrathin FET of a first polarity type and including a gate, a source and a drain, the source being coupled to a first control line;
• a second FET being an ultrathin FET of a second polarity type and including a gate, a source and a drain, the source of the second FET being coupled to the gate of the first FET, the gate of the second FET being coupled to the drain of the first FET and the source of the second FET being coupled to a first potential;
• a first load device coupled between a second potential and the gate of the first FET;
• and
• a second load device coupled between the gate of the second FET and a second control line.

A SRAM array forming a memory comprising a first line having a first potential, a second line having a second potential, a plurality of row lines, a plurality of column lines and a plurality of memory cells, each memory cell of the plurality comprising:

• a first switching device having a control terminal and first and second load terminals, a first of the load terminals being coupled to one of the plurality of row lines;
• a first load element having a first terminal coupled to the second load terminal and having a second terminal coupled to one of the plurality of column lines;
• and
• a second switching device having a control terminal and first and second load terminals, the first load terminal of the second switching device being coupled to the control terminal of the first switching device, the second load terminal of the second switching device being coupled to the first line and the control terminal of the second switching device being coupled to the second load terminal of the first switching device;
• and
• a second load element having a first terminal coupled to the second line and a second terminal coupled to the second load terminal of the second switching device.

A computer system comprising:

• a central processing unit;
• an input interface coupled to the central processing unit;
• and
• a memory device coupled to the central processing unit, the memory device storing instructions and data for use by the central processing unit, wherein the memory device includes a SRAM array formed from cells each including in combination:
• a first load device;
• a first ultrathin transistor having a power electrode coupled to the first load device;
• a second load device;
• and
• a second ultrathin transistor including a power electrode coupled to the second load device, wherein the first load device is merged with a control electrode of the second ultrathin transistor and vice versa.

A process for forming a SRAM cell having an area of 8F2, or less, wherein F represents one-half of a minimum lithographic pitch of the SRAM cell, the process comprising:

• providing a semiconductive substrate having a first conductivity type:
• forming a diffusion region of a second conductivity type different than the first conductivity type in the substrate, the diffusion region being configured to act as a row address line;
• forming first and second dielectric pillars on the substrate, the first and second pillars having respective plan view areas of about F2 and being separated by a distance of about F, one of the first and second pillars being formed atop the diffusion region and another of the first and second pillars not being formed atop the diffusion region;
• and
• forming first and second ultrathin transistors and first and second load devices in a space between the first and second pillars, the first load device being merged with the second ultrathin transistor and the second load device being merged with the first ultrathin transistor.