Stacked 1t-nmtj mram structure

A semiconductor device, comprising:

• an access transistor layer comprising a plurality of access transistors each electrical contact with a respective bit line;
• a plurality of memory array layers, each provided vertically over said acc transistor layer, said memory array layers comprising a plurality of memory cells and a respective a sense line for each of said plurality MRAM memory cells, said MRAM memory cells being arranged wi the array layers to define sets of MRAM memory cells in a direction perpendicular to a planar direction of said array layers;
• and
• a plurality of sense line interconnects, wherein each said sense line interconnect is in electrical contact with a respective access transisto said plurality of access transistors and with one said sense line of eac said memory array layers.

A memory device, comprising:

• a first memory array layer comprising a first MRAM memory cell, said fi MRAM memory cell being associated with a first sense line;
• a second memory array layer over said first memory array layer and comprising a second MRAM memory cell, wherein said second MR memory cell is located above said first MRAM memory cell and is associated with a second sense line;
• and
• an access transistor layer comprising a first access transistor, said first ac transistor, when turned on, coupling a first bit line with said first an second sense lines.

A semiconductor device, comprising:

• a first access transistor layer comprising a plurality of access transistors;
• a first memory array layer comprising a plurality of first MRAM memo each of said plurality of first MRAM memory cells being defined at a plurality of first intersection points of a plurality of first common li and a plurality of first sense lines;
• a second memory array layer provided over said first memory array layer comprising a plurality of second MRAM memory cells, each of said plurality of second MRAM memory cells being defined at one of a plurality of second intersection points of a plurality of second comm lines and a plurality of second sense lines;
• and
• a plurality of sense line interconnects, each one of said plurality of sense interconnects being in electrical contact with the respective first sens line, the respective second sense line, and with one of said plurality access transistors.

An MRAM read architecture, comprising:

• an access transistor;
• a series of n magnetic bits each having a magnetic tunnel junction and t associated with a respective sense line, said series of n magnetic bits in a substantially columnar stack over said access transistor, n being to or greater than 2;
• and
• an interconnect in electrical contact with each said respective sense line said series of n magnetic bits and with said access transistor.

A processor system, comprising:

• a processor;
• and
• an MRAM memory circuit, comprising:
• a first memory array layer comprising a first MRAM memory cell, said f MRAM memory cell being associated with a first sense line;
• a second memory array layer over said first memory array layer and comprising a second MRAM memory cell, wherein said second MR memory cell is located above said first MRAM memory cell and is associated with a second sense line;
• and
• an access transistor layer comprising a first access transistor, said first an transistor, when turned on, coupling a first bit line with said first an second sense lines.

A method of fabricating a memory device, comprising:

• providing a substrate;
• forming an access transistor on said substrate, said access transistor havi first and a second active area;
• providing a bit line in electrical contact with said access transistor at sai active area;
• providing an interconnect in electrical contact with said access transisto said second active area;
• forming a first magnetic bit over said access transistor;
• forming a first sense line associated with said first magnetic bit, which i
• electrical contact with said interconnect;
• forming a second magnetic bit over said first magnetic bit;
• and
• forming a second sense line associated with said second magnetic bit, w is in electrical contact with said interconnect.

A method of forming an MRAM device, comprising:

• providing a sense amplifier;
• providing an interconnect;
• providing an access transistor capable of electrically connecting said sen amplifier and said interconnect;
• providing n array planes over said access transistor, each of said n array comprising at least one MRAM memory cell, said at least one MRA memory cell comprising a common line, wherein n is equal to 2 or greater;
• and
• providing a plurality of sense lines, each associated with a respective sai least one MRAM memory cell of said n array planes and being in electrical contact with said interconnect.

A method of reading memory stored in an MRAM cell, comprising:

• selecting a common line associated with a respective magnetic bit of a plurality of magnetic bits, wherein each one of said plurality of mag bits is in a respective plane of magnetic bits and is associated with a respective sense line;
• selecting a wordline of an access transistor, said access transistor being electrically coupled to each said respective sense line;
• and
• sensing a resistance state of said respective magnetic bit associated with common line at a bit line coupled to said access transistor.