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US 2003/0214833 A1Published application
Sram with improved noise sensitivity
AssigneeInternational Business Machines Corporation
InventorsLouis L. Hsu, Rajiv V. Joshi, Robert C. Wong
Life of this patent
Estimating the term…
Abstract
A static random access memory (SRAM) with cells in one portion having a higher beta ratio than the remaining cells of the array. In a first portion, cells have a low β ratio for high performance. A second portion of the array contains SRAM cells with a higher β ratio that are more stable than the cells in the first portion, but are somewhat slower.
Claims26
A static random access for memory (SRAM) comprising:
- an array of SRAM cells, a first array portion including said SRAM cells having a first beta ratio for performance and density;
- and
- a second array portion including SRAM cells having a second beta ratio higher than said first beta ratio, cells of said second array portion being more stable than cells of said first array portion.
A static random access for memory (SRAM) comprising:
- an array of SRAM cells, a first array portion including said SRAM cells having a first beta ratio for performance and density;
- a second array portion including SRAM cells having a second beta ratio higher than said first beta ratio, cells of said second array portion being more stable than cells of said first array portion;
- a word decode selecting one word line amongst a plurality of word lines, each selected word line selecting a plurality of SRAM cells from said array;
- and
- a column select for selecting a column amongst a plurality of columns, a cell at a selected column and word line being accessed.
2 more elements
A static random access for memory (SRAM) comprising:
- an array of SRAM cells, a first array portion including said SRAM cells having a first beta ratio for performance and density;
- a second array portion including SRAM cells having a second beta ratio higher than said first beta ratio, cells of said second array portion being more stable than cells of said first array portion;
- a word decode selecting one word line amongst a plurality of word lines, each selected word line selecting a plurality of SRAM cells from said array;
- a column select for selecting a column amongst a plurality of columns, a cell at a selected column and word line being accessed;
- and
- a column supply voltage select, said column supply voltage select providing a first voltage level to an unselected column and a second voltage supply level to a selected column whereby said second supply voltage provides a lower effective beta ratio to cells in said column than said first supply voltage.
3 more elements
A static random access for memory (SRAM) comprising:
- an array of SRAM cells, a first array portion including said SRAM cells having a first beta ratio for performance and density;
- a second array portion including SRAM cells having a second beta ratio higher than said first beta ratio, cells of said second array portion being more stable than cells of said first array portion;
- a first word decode selecting one word line amongst a plurality of word lines, each selected word line selecting a plurality of SRAM cells from said array;
- a column select for selecting a column amongst a plurality of columns, a cell at a selected column and word line being accessed;
- and
- a second word decode selecting one word line amongst a plurality of word lines in said second array portion, whereby sensitive data is selectively transferred between said first array portion and said second array portion depending upon a need for additional stability or performance.
3 more elements
Dependencies are inferred from the claim text.