Semiconductor memory device switchable to twin memory cell configuration

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns;
• a plurality of word lines arranged along the row direction;
• a plurality of bit line pairs arranged along the column direction;
• and
• a decoder for selecting a word line and a bit line pair corresponding to an address signal specifying each of said plurality of memory cells among said plurality of word lines and said plurality of bit line pairs, respectively;
• wherein
• when a twin cell mode signal for storing memory data corresponding to 1 bit of memory information represented as binary information by using two memory cells is activated,
• said decoder selects the word line and the bit line pair for activating said two memory cells, and
• said two memory cells store said memory data and an inverted data of said memory data, respectively.