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US 2003/0214828 A1Published application
Read-only memory with reduced loading value
AssigneeMacronix International Co., Ltd.
InventorShi-Xian Chen
Life of this patent
Estimating the term…
Abstract
By adding multiple rows of auxiliary switches and then multiple current paths a read only memory circuit can be formed to reduce loading values when reading a specific memory cell. Therefore, the current can be increased, and the error probability of the sense amplifier can be reduced when reading a specific memory cell.
Claims10
A read-only memory including a plurality of word lines and K memory banks, each word line being parallel to each other and one of the K memory banks being an n memory bank, the nth memory bank comprising:
- a first main bit line BL(n);
- a first selecting line and a second selecting line, which are perpendicular to the first main bit line BL(n);
- a plurality of first selecting sWitches and a plurality of second selecting switches that are controlled by the first selecting line and second selecting line respectively;
- a first sub-bit line SB1(n), a second sub-bit line SB2(n), a third sub-bit line SB3(n), and a fourth sub-bit line SB4(n), wherein when the first selecting switches are turned on, the first main bit line BL(n) is electrically connected to the second sub-bit line SB2(n) and the third sub-bit line SB3(n);
- when the second selecting switches are turned on, the first main bit line BL(n) is electrically connected to the third and fourth sub-bit lines SB3(n) and SB4(n) respectively;
- a plurality of first auxiliary switches and a plurality of second auxiliary switches, wherein the first auxiliary switches are controlled by a first auxiliary line SL1 and the second auxiliary switches are controlled by the second auxiliary line SL2, and wherein at least some of the first and the second auxiliary switches have low threshold voltage;
- and
- a plurality of memory cells, which are controlled by a plurality of word lines, and each memory cell is connected between two adjacent sub-bit lines;
- wherein when a current flows through one of the memory cells, the current at least flow through one of the first or the second auxiliary switches that are turned on.
6 more elements
A method of reading a read-only memory, wherein the read-only memory includes a plurality of word lines which are parallel to each other, and the read-only memory includes K memory banks, one of the K memory banks is an nth memory bank, and the nth memory bank includes:
- a first main bit line BL(n), a second main bit line GL(n), and a first, second, third, and fourth sub-bit lines SB1(n)˜SB4(n);
- a first and a second selecting lines, which are perpendicular to the first main bit line BL(n);
- a plurality of first and second selecting switches, which are respectively controlled by the first and the second selecting lines;
- a plurality of first and second auxiliary switches, which are respectively controlled by a first auxiliary line ALl and a second auxiliary line AL2, and at least some of the first and the second auxiliary switches have low threshold voltage;
- and
- a plurality of memory cells, which are controlled by the word lines with each memory cell connected between two adjacent sub-bit lines;
- the method of reading one of the memory cells chosen from the nth memory bank of the read-only memory comprises:
- driving the first main bit line BL(n) by a sense amplifier, and connecting a second main bit line GL(n+1) of a (n+1)th memory bank to a ground end;
- enabling the word line corresponding to the chosen memory cell;
- enabling the first selecting line or the second selecting line corresponding to the chosen memory cell in order to turn on the first selecting switch or second selecting switches, wherein when the first selecting switches are turned on, the first main bit line BL(n) is electrically connected to the second sub-bit line SB2(n) and the third sub-bit line SB3(n), and when the second selecting switches are turned on, the first main bit line is electrically connected to the third sub-bit line SB3(n) and the fourth sub-bit line SB4(n);
- enabling the third selecting line or fourth selecting line corresponding to the chosen memory cell in order to turn on the third selecting switches or fourth selecting switches, wherein when the third selecting switches are turned on, the second main bit line GL(n+1) is electrically connected to the fourth sub-bit line SB4(n) and a first sub-bit line SB1(n+1) of a (n+1)th memory bank, and when the fourth selecting switches are turned on, the second main bit line GL(n+1) is electrically connected to the first sub-bit line SB(n+1) and the second sub-bit line SB2(n+1);
- and
- enabling the first auxiliary line ALl or the second auxiliary line AL2 corresponding to the chosen memory cell in order to turn on the first or second auxiliary switches;
- wherein when a current flows through the chosen memory cell, the current should at least flow through one of the first or second auxiliary switches that are turned on.
11 more elements
Dependencies are inferred from the claim text.