Method and system for disabling a scanout line of a register flip-flop

The flip-flop of claim 1, further comprising at least one latch, said circuit being coupled between the scan output and the at least one latch.

The flip-flop of claim 1, further comprising a data output for providing the value stored in the flip-flop, said circuit being coupled between the data output and the scan output.

4 The flip-flop of claim 3, wherein the circuit comprises at least one pass gate transistor coupled between the data output of the flip-flop and the scan output so that the scan output selectively follows the data output of the flip-flop.

The flip-flop of claim 1, wherein the circuit drives said scan output to a predetermined logic value when the flip-flop is in the normal mode of operation.

7 The flip-flop of claim 5, wherein the circuit comprises a pull up transistor coupled to the scan output for selectively driving the scan output to a high logic value

The flip-flop of claim 1, wherein the flip-flop is a D-flip-flop.

The flip-flop of claim 1, further comprising a data output for outputting the logic value stored in the flip-flop, wherein the circuit comprises a logic gate having a first input coupled to a data output of the flip-flop and an output coupled to the scan output for generating an output logic value

10 The flip-flop of claim 9, wherein a second input of the logic gate is coupled to the mode configuration input.

The integrated circuit of claim 11, wherein said at least one flip-flop of each register comprises at least one pass gate transistor coupled between the data output and the scan output of the flip-flop for selectively providing, by the scan output, the logic value stored by the flip-flop

The integrated circuit of claim 11, wherein the scan output of the at least one flip-flop of each register is driven to a predetermined logic value when in the normal mode of operation.

The integrated circuit of claim 11, wherein the at least one flip-flop of each register comprises a logic gate having a first input coupled to a data output of the flip-flop, a second input of the logic gate coupled to the test enable input and an output coupled to the scan output.

A method for operating a flip-flop having serial scan capabilities including a scan output, said method comprising the steps of:

• receiving a mode configuration signal for configuring the flip-flop between a test mode of operation and a normal mode of operation;
• and
• selectively disabling the scan output from providing the logic value stored by the flip-flop based upon the value of the mode configuration signal received.