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US 2003/0213997 A1Published application
Asymmetrical MOSFET layout for high currents and high speed operation
AssigneeInternational Business Machines Corporation
InventorsScott M. Parker, Steven J. Tanghe
Life of this patent
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Abstract
A structure and method for a field effect transistor capable of handling high currents, comprises interleaved source and drain diffusion regions with drain diffusion contacts to a first metal level over the drain diffusions only; while a second metal level covers the full width of the device and takes current out of the source in a primarily vertical direction.
Claims22
A field effect transistor comprising:
- a drain comprising a first diffusion region and a first metal;
- a source comprising a second diffusion region and a second metal, wherein said source is larger in size than said drain;
- and
- a source connection comprising a third metal connected to said second metal.
1 more element
A MOSFET device comprising:
- a drain comprising a first diffusion region and a first metal;
- a source comprising a second diffusion region and a second metal level, wherein said source is larger in size than said drain;
- and
- a source connection comprising a third metal connected to said second metal.
1 more element
A field effect transistor comprising:
- an interleaved source diffusion region and drain diffusion region;
- a plurality of drain diffusion contacts to a first metal level, wherein said drain diffusion contacts are over said drain diffusion region only;
- and
- a second metal level dimensioned to cover a width of said field effect transistor,
- wherein said second metal level takes current out of said source region in a substantially vertical direction, wherein said vertical direction is a direction perpendicular to a plane of said second metal level.
2 more elements
A field effect transistor comprising:
- an interleaved source diffusion region and drain diffusion region;
- a plurality of source diffusion contacts to a first metal level, wherein said source diffusion contacts are over said source diffusion region only;
- and
- a second metal level dimensioned to cover a width of said field effect transistor,
- wherein said second metal level takes current out of said drain region in a substantially vertical direction, wherein said vertical direction is a direction perpendicular to a plane of said first metal level.
2 more elements
A method for forming a field effect transistor, said method comprising:
- forming a drain region, wherein said drain region comprises a first diffusion region and a first metal;
- forming a gate region adjacent said drain region;
- forming a source region, wherein said source region comprises a second diffusion region and a second metal;
- configuring said source region to be smaller in size than said drain region;
- and
- forming a source connection comprised of a third metal connected to said second metal.
3 more elements
Dependencies are inferred from the claim text.