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OwnerSubramanian Karthikeyan, Sailesh Mansinh Merchantinventors
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An interconnect structure of a semiconductor device designed for reduced intralevel and interlevel capacitance, and includes a lower metal layer and an upper metal layer and an insulating layer interposed between metal layers. Each of the lower metal layer and upper metal layer include a plurality of conductive lines spaced apart and extending within a low-k dielectric material. A plurality of metal-filled vias interconnects the conductive lines of the lower metal layer to the conductive lines of the upper metal layer. The insulating layer comprises also comprises a low-k dielectric material disposed between the adjacent metal-filled vias. Openings, having been etched in the low-k dielectric material between the conductive lines of the upper and lower metal layers, and the metal-filled vias, an ultra-low k material is deposited within the openings. The integration of the ultra-low k and low-d dielectric materials reduces the overall capacitance of the structure to enhance performance.
An interconnect structure of a semiconductor device, comprising:
The interconnect structure of 2 wherein said ultra low-k dielectric filled trenches include trenches extending from the upper metal layer to a predetermined depth of the insulating layer, which trenches extend between the metal lines in the upper metal layer and the metal-filled vias in the insulating layer.
A dual damascene interconnect structure of a semiconductor device, said interconnect structure, comprising:
An interconnect structure of a semiconductor device, comprising:
A dual damascene method of making a semiconductor device having an interconnect structure, comprising the steps of:
A method of making a semiconductor device having an interconnect structure, comprising the steps of:
Dependencies are inferred from the claim text.