Loading patent…
OwnerShen Lin, Andrew Yang +1inventors
InventorsShen Lin, Andrew Yang, Norman Chang
Estimating the term…
Methods for efficient integrated circuit (“IC”) dynamic IR-drop analysis algorithm are disclosed. In one aspect, the disclosed methods eliminate the need for peak-power input stimulus vectors or Verilog's value change dump (“VCD”). Rather than performing transient simulation over a long set of input vectors to determine the worst dynamic IR, the disclosed method statistically determines the switching direction and the timing for each instance based on its block or module switching scenario. Full-chip transient simulation, including the RLC extracted from the power-ground network, is then performed accordingly over a few clock cycles. This approach makes feasible full-chip dynamic IR-drop verification with the consideration of power-ground inductance and capacitance. Furthermore, methods are disclosed for optimal decoupling-capacitor insertion for remedying power-integrity problems, including their amounts and locations.
A method for determining instance switching in simulating integrated circuit design, comprising the steps of:
A method for simulating integrated circuit design, comprising the steps of:
A method for selecting and determining switching instances and switching probabilities in simulating integrated circuit design, said design comprising of a plurality of blocks, comprising the steps of:
A method for determining decoupling capacitor insertion in an integrated circuit design, comprising the steps of:
A method for determining decoupling capacitor insertion in an integrated circuit design, comprising the steps of:
Dependencies are inferred from the claim text.