Unconventional clocked circuit components having multiple timing models
AssigneeTranslogic Technology, Inc.
InventorDzung Joseph Tran
Life of this patent
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Abstract
A flip-flop is characterized at a given voltage, temperature, and process corner by generating a plurality of rise time setup tables for the flip-flop, generating a plurality of fall time setup tables for the flip-flop, generating a plurality of rise time CQ tables for the flip-flop, and generating a plurality of fall time CQ tables for the flip-flop. The multiple tables are included in at least one library.
Claims36
A method of characterizing a flip-flop at a particular voltage, temperature, and process corner, the method comprising:
- at each of a plurality of points of a CQ sensitivity range of the flip-flop, generating a plurality of tables, each table comprising at least one of a plurality of propagation delays and a plurality of setup times for the flip-flop;
- and
- including the tables in at least one library.
A method of characterizing a clocked component at a particular voltage, temperature, and process corner, the method comprising:
- at each of a plurality of points of a CQ sensitivity range of the component, generating multiple timing models, each timing model comprising at least one of a plurality of propagation delays and a plurality of setup times for the component;
- and
- including the timing models in at least one library.
An article comprising:
- a machine-readable media comprising data representing at least one component libraries, the at least one libraries comprising
- multiple timing models at different points of a CQ sensitivity of a component;
- each timing model comprising at least one of a plurality of propagation delays and a plurality of setup times for the component;
- the multiple timing models for a single netlist for the component.
An article comprising:
- a machine-readable media comprising at least one component libraries, the at least one libraries comprising:
- multiple tables generated at each of a plurality of points of a CQ sensitivity range of a flip-flop, the multiple tables generated at a particular voltage, temperature, and process corner of the flip-flop and from the same netlist for the flip-flop, each table comprising at least one of a plurality of propagation delays and a plurality of setup times for the flip-flop.
A method of characterizing a flip-flop at a given voltage, temperature, and process corner, the method comprising:
- generating a plurality of rise time setup tables for the flip-flop;
- generating a plurality of fall time setup tables for the flip-flop;
- generating a plurality of rise time CQ tables for the flip-flop;
- generating a plurality of fall time CQ tables for the flip-flop;
- and
- including the multiple tables in at least one library.
An article comprising:
- a machine-readable media comprising at least one component libraries, the at least one libraries comprising tables generated at a particular voltage, temperature, and process corner of a flip-flop, the at least one libraries comprising:
- a plurality of rise time setup tables for a flip-flop;
- a plurality of fall time setup tables for the flip-flop;
- a plurality of rise time CQ tables for the flip-flop;
- and
- a plurality of fall time CQ tables for the flip-flop;
- the tables generated from the same at least one of a SPICE netlist and a GDSII netlist.
Dependencies are inferred from the claim text.