Method and apparatus for minimizing clock skew in a balanced tree when interfacing to an unblalanced load
AssigneeAgilent Technologies, Inc.
InventorsRichard S. Rodgers, Scott T. Evans
Life of this patent
Estimating the term…
Abstract
A method for minimizing clock skew in a balanced tree when interfacing to an unbalanced load is presented. Unused portions of the balanced tree are replaced by a loading equivalent circuit to create a physically balanced load. In the preferred embodiment, the loading equivalent circuit is implemented with a single-pole resistor-capacitor circuit that has been modeled to match the RC characteristics of the replaced branch of the tree.
Claims13
A method for minimizing clock skew in an integrated circuit, comprising:
- designing a balanced clock tree, said balanced clock tree comprising a plurality of branches each characterized by a load resistance and load capacitance;
- replacing a branch of said balanced clock tree with a loading equivalent circuit, said loading equivalent circuit characterized by said load resistance and said load capacitance of said replaced branch.
A semi-balanced signal routing tree for an integrated circuit, comprising:
- a node of an interconnect routing tree of said integrated circuit;
- a plurality of metal routing trace branches branching from said node, wherein at least one of said branches comprises a balanced branch characterized by a load resistance and a load capacitance and at least one of said branches comprises a loading equivalent circuit characterized by said load resistance and said load capacitance of said balanced branch.
An integrated circuit comprising a semi-balanced signal routing tree, comprising:
- circuitry which receives a predetermined signal;
- at least one signal interconnect layer for routing said predetermined signal;
- a node on said at least one interconnect layer;
- a plurality of branches comprising a plurality of metal signal routing traces for routing said predetermined signal, each branching from said node, wherein at least one of said branches comprises a balanced branch characterized by a load resistance and a load capacitance and at least one of said branches comprises a loading equivalent circuit characterized by said load resistance and said load capacitance of said balanced branch.
Dependencies are inferred from the claim text.