Emulating multiple bus used within a data processing system
AssigneeArm Limited
InventorsAndrew Mark Nightingale, Timothy Charles Mace
Life of this patent
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Abstract
A test system for data processing circuit design emulates multiple bus masters and provides an arbitration mechanism for coordinating arbitration between those bus masters in the design emulation. The shared bus being tested may be a multi-layer bus and one or more of the bus masters being emulated or bus slaves being emulated may be cut-down emulations modelling the bus interaction itself or full emulations of the intended bus master circuit or bus slave circuit including its operational data processing.
Claims18
A method of testing a design of a data processing circuit having a plurality of bus masters connected via a shared bus to at least one bus slave, said method comprising the steps of:
- emulating a bus master issuing a bus access request to make a data transfer via said shared bus to a bus slave;
- detecting if another bus master being emulated has blocked access to said bus slave;
- and
- if another bus master being emulated has blocked access to said bus slave, then refusing said bus access request;
- or
- if another bus master being emulated has not blocked access to said bus slave, then granting said bus access request.
Apparatus for testing a design of a data processing circuit having a plurality of bus masters connected via a shared bus to at least one bus slave, said apparatus comprising:
- an emulator operable to emulate a bus master issuing a bus access request to make a data transfer via said shared bus to a bus slave;
- and
- a detector operable to detect if another bus master being emulated has blocked access to said bus slave;
- wherein
- if another bus master being emulated has blocked access to said bus slave, then said bus access request is refused;
- or
- if another bus master being emulated has not blocked access to said bus slave, then said bus access request is granted.
Dependencies are inferred from the claim text.