Method and apparatus for custom design in a standard cell design environment

A method of converting a SPICE netlist to a standard cell netlist comprising:

• converting said SPICE netlist to an HDL netlist;
• synthesizing said HDL netlist to produce a standard cell netlist;
• extracting timing paths from said SPICE netlist;
• simulating said SPICE netlist;
• extracting timing information from the SPICE simulation;
• and
• creating a standard delay file that reflects said timing information such that when applied to said standard cells, standard cell timing approximates that of said SPICE simulation.

A method of designing an integrated circuit containing standard cell and custom logic comprising:

• designing a first portion of said integrated circuit using HDL to produce an HDL netlist;
• designing a second portion of said integrated circuit using SPICE to produce a SPICE netlist;
• synthesizing said HDL netlist to produce a first standard cell netlist;
• converting said SPICE netlist to logic functions;
• selecting standard cells that correspond to said logic functions to produce a second standard cell netlist;
• extracting timing paths from said SPICE netlist;
• simulating said SPICE netlist;
• extracting timing information from the SPICE simulation;
• and
• creating a standard delay file that reflects said timing information such that when applied to said standard cells in said second standard cell netlist, standard cell timing approximates that of said SPICE simulation.

A method of designing an integrated circuit containing standard cell and custom logic comprising:

• designing a first portion of said integrated circuit using HDL to produce a first HDL netlist;
• designing a second portion of said integrated circuit using SPICE to produce a SPICE netlist;
• synthesizing said first HDL netlist to produce a first standard cell netlist;
• converting said SPICE netlist to a second HDL netlist;
• synthesizing said second HDL netlist to produce a second standard cell netlist;
• extracting timing paths from said SPICE netlist;
• simulating said SPICE netlist;
• extracting timing information from the SPICE simulation;
• and
• creating a standard delay file that reflects said timing information such that when applied to said standard cells in said second standard cell netlist, standard cell timing approximates that of said SPICE simulation.

An integrated circuit produced by the steps of:

• partitioning a design into a plurality of function blocks;
• designing a first one of said plurality of function blocks employing an HDL to produce an HDL netlist;
• synthesizing said HDL netlist to produce a first standard cell netlist;
• designing a second one of said plurality of function blocks employing SPICE to produce a SPICE netlist;
• simulating said SPICE netlist;
• converting said SPICE netlist to logic functions;
• selecting standard cells that correspond to said logic functions to produce a second standard cell netlist;
• extracting timing paths from said SPICE netlist;
• extracting timing information from the SPICE simulation;
• and
• creating a standard delay file that reflects said timing information such that, when applied to said standard cells in said second standard cell netlist, standard cell timing approximates that of said SPICE simulation.

An integrated circuit produced by the steps of:

• partitioning a design into a plurality of function blocks;
• designing a first one of said plurality of function blocks employing an HDL to produce a first HDL netlist;
• synthesizing said first HDL netlist to produce a first standard cell netlist;
• designing a second one of said plurality of function blocks employing SPICE to produce a SPICE netlist;
• simulating said SPICE netlist;
• converting said SPICE netlist to HDL to produce a second HDL netlist;
• synthesizing said second HDL netlist to produce a second standard cell netlist;
• extracting timing paths from said SPICE netlist;
• extracting timing information from the SPICE simulation;
• and
• creating a standard delay file that reflects said timing information such that when applied to said standard cells in said second standard cell netlist, standard cell timing approximates that of said SPICE simulation.

A system for converting a SPICE netlist to a standard cell netlist comprising:

• a computer;
• a first program that converts said SPICE netlist to logic functions;
• a second program that selects standard cells corresponding to said logic functions;
• a third program that correlates SPICE simulation timing information with signal paths of said standard cells and creates a standard delay file such that when applied to said standard cells, timing of said standard cells approximates that of said SPICE simulation.

A system for converting a SPICE netlist to a standard cell netlist comprising:

• a computer;
• a first program that converts said SPICE netlist to logic functions;
• a second program that employs SPICE simulation information to select standard cells for said logic functions that reflect timing information;
• a third program that correlates SPICE simulation timing information with signal paths of said standard cells and creates a standard delay file such that when applied to said standard cells, timing of said standard cells approximates that of said SPICE simulation.

A system for converting a SPICE netlist to a standard cell netlist comprising:

• a computer;
• a first program that converts said SPICE netlist to an HDL netlist;
• a second program that synthesizes said HDL netlist into a standard cell netlist comprising a plurality of standard cells;
• and
• a third program that correlates SPICE simulation timing information with signal paths of said standard cells and creates a standard delay file such that when applied to said standard cells, timing of said standard cells approximates that of said SPICE simulation.