Calculation circuit for calculating a sampling phase error

Calculation circuit for calculating a sample phase error signal for a decision feedback clock phase regulation circuit, having:

• (a) a subtraction circuit (30) which generates a differential signal between a digital received signal (zk), equalized by an equalizer, and a digital estimate â(K) formed by a decision device;
• (b) a nonrecursive digital filter (43) for filtering the differential signal (ek),
• the nonrecursive digital filter (43) having a delay element chain (32) with a number of serially connected delay elements (32-i) whose delayed output signals are multiplied in each case by an adjustable weighting coefficient and are added by an adder (41) to a digital filter output signal,
• the weighting coefficient for the output signal of the delay element situated in the middle of the delay element chain (32) being zero;
• (c) a delay circuit (31) for delaying the digital estimate signal a (K) with a delay time (M*T) between an input of the nonrecursive digital filter (43) and the delay element, situated in the middle, inside the delay element chain (32), and having
• (d) a multiplier (47) which multiplies the digital filter output signal of the nonrecursive digital filter (43) by the output signal of the delay circuit (31) to form the sampling phase error signal vk.

Clock phase regulation circuit for clock phase regulation, having:

• (a) an analog-to-digital converter (10) which samples an analog received signal with the aid of a sampling rate signal in order to generate a digital received signal;
• (b) an equalizer (16) for equalizing the digital received signal;
• (c) a decision device (18) which is connected downstream of the equalizer (16) and generates a digital estimate signal âK for the received signal from the equalized digital received signal;
• (d) a sampling phase error detector (1) for generating a sample phase error signal vk for clock phase regulation, which specifies the phase deviation between the signal phase of the sampling rate signal and a setpoint signal phase of an ideal sampling rate signal;
• and having
• (e) a loop filter (26) which filters the sampling rate error signal vk and supplies it as a sample signal to the analog-to-digital converter (10);
• (f) the sampling phase error detector (1) having:
• a subtraction circuit (30) which generates a differential signal ek between the equalized digital received signal zk and the digital estimate signal âK,
• a first delay element chain (31) which has a plurality of serially connected delay elements, for delaying the digital estimate âK of the decision device,
• a second delay element chain (32), which has a plurality of serially connected delay elements, for delaying the equalized differential signal ek,
• a multiplier array (33) which consists of multipliers arranged in matrix form and which multiplies the undelayed digital estimate âK and the delayed estimates of all the delay elements of the first delay element chain by the equalized differential signal ek and the delayed differential signals of all the delay elements of the second delay element chain in order to generate product signals,
• a weighting circuit (39) which multiplies the product signals generated by the multiplier array by adjustable weighting factors,
• and an adder (41) which adds the product signals weighted by the weighting circuit in order to generate the sampling phase error signal vk, which is supplied to the loop filter (26) via a signal output (24) of the sampling phase error detector (1).