Interface architecture for embedded field programmable gate array cores

Abstract

An interface architecture is presented for Field Programmable Gate Array (FPGA) cores by which an FPGA core can be embedded into an integrated circuit and easily configured and tested without detailed knowledge of the FPGA core. A microcontroller coupled to the FPGA core has a general instruction set that provides access to all resources within the FPGA core. This enables high level services, such as configuration loading, configuration monitoring, built in self test, defect analysis, and debugger support, for the FPGA core upon instructions from a host interface. The host interface, which modifies the instructions from a processor unit, for example, for the microcontroller, provides an adaptable buffer unit to allow the FPGA core to be easily embedded into different integrated circuits.

Dependencies are inferred from the claim text.