US 2003/0212935 A1 · Circuit and method for accelerating the test time of a serial access memory device

Abstract

A serial memory device includes a test mode for accelerating the writing of externally-supplied data into the memory array by ganging column address so that a single clock writes a single row. Data is retrieved from the memory either by singularly addressed locations or by mirrored address locations across a memory boundary with retrieved data being individually compared via logic asserted during testing operations. Depending on the requested test mode, the compare results can return an order for continuance of array testing or insertion of complemented data into the currently-compared memory location and continuance of array testing. A GO/No Go indication is provided via output circuitry controlled by the test mode.

Claims21

Dependent claims

A serial memory comprising:

a left memory array;
a right memory array;
a left shift register coupled to the left memory array;
a right shift register coupled to the right memory array;
a left latch for receiving externally applied compare data;
a right latch for receiving externally applied compare data;
a left complement switch coupled to the left latch;
a right complement switch coupled to the right latch;
a left comparator for comparing data from the left shift register to data from the left complement switch;
a right comparator for comparing data from the right shift register to data from the right complement switch;
and
an error detecting multiplexer coupled to the left and right comparators for providing an output error signal.

9 more elements

Dependencies are inferred from the claim text.

Circuit and method for accelerating the test time of a serial access memory device

Life of this patent

Circuit and method for accelerating the test time of a serial access memory device

Life of this patent

Abstract

Claims21