Debug port for on-die dram

A cache memory, comprising:

• a communications switch have a plurality of normal ports and at least one debug port, said switch being operable in a normal mode or a debug mode;
• a plurality of storage units each comprising a DRAM array coupled to a DRAM controller, each of said storage units being coupled to a respective normal port of said switch;
• a cache controller for controlling information transfer to and from said plurality of storage units while said communications switch is in the normal mode, said cache controller coupled to said communications switch via at least one of said normal ports;
• and
• a debug port controller for controlling information transfer to and from said plurality of storage units while said communications switch is in the debug mode, said debug port controller coupled to said communications switch via one of said at least one debug port.

A bus bridge, comprising:

• a bridge communication switch;
• a host interface, coupled to said bridge communication switch, for interfacing said bus bridge to a host bus;
• a memory controller, coupled to said bridge communication switch for interfacing said bus bridge to a memory bus;
• a memory interface coupled to said memory controller;
• a cache coupled to said memory controller, wherein said cache further comprises,
• a cache communications switch have a plurality of normal ports and at least one debug port, said switch being operable in a normal mode or a debug mode;
• a plurality of storage units each comprising a DRAM array coupled to a DRAM controller, each of said storage units being coupled to a respective normal port of said cache communication switch;
• a cache controller for controlling information transfer to and from said plurality of storage units while said cache communications switch is in the normal mode, said cache controller coupled to said cache communications switch via at least one of said normal ports;
• and
• a debug port controller for controlling information transfer to and from said plurality of storage units while said cache communications switch is in the debug mode, said debug port controller coupled to said communications switch via one of said at least one debug port.

A method for writing a memory subsystem having a plurality of memory arrays, comprising:

• activating a debug port controller coupled to a communication switch;
• transferring write data to a storage in said debug port controller;
• identifying the memory array to be written;
• identifying an address within the memory array to be written;
• transferring write data from said storage to said identified memory array via said switch.

A method of reading a memory subsystem having a plurality of memory arrays, comprising:

• activating a debug port controller coupled to a communication switch;
• identifying the memory array to be written;
• identifying an address within the memory array to be written;
• transferring read data to a storage in said debug port controller;
• transferring read data from said storage to a buffer outside the memory subsystem.

A memory system comprising:

• a switch;
• at least one memory array coupled to a first port of said switch;
• a first memory controller for accessing said at least one memory array through a second port of said switch;
• and
• a second memory controller for accessing said at least one memory array through a third port of said switch.

A processing system, comprising:

• a processor;
• a memory system, coupled to said processor, said memory system further comprising,
• a switch;
• at least one memory array coupled to a first port of said switch;
• a first memory controller for accessing said at least one memory array through a second port of said switch;
• and
• a second memory controller for accessing said at least one memory array through a third port of said switch.

A system, comprising:

• a local bus;
• a processor coupled to said local bus;
• a bus bridge coupled to said local bus, wherein said bus bridge further comprises,
• a bridge communication switch;
• a host interface, coupled to said bridge communication switch, for interfacing said bus bridge to a host bus;
• a memory controller, coupled to said bridge communication switch for interfacing said bus bridge to a memory bus;
• a memory interface coupled to said memory controller;
• a cache coupled to said memory controller, wherein said cache further comprises,
• a cache communications switch have a plurality of normal ports and at least one debug port, said switch being operable in a normal mode or a debug mode;
• a plurality of storage units each comprising a DRAM array coupled to a DRAM controller, each of said storage units being coupled to a respective normal port of said cache communication switch;
• a cache controller for controlling information transfer to and from said plurality of storage units while said cache communications switch is in the normal mode, said cache controller coupled to said cache communications switch via at least one of said normal ports;
• and
• a debug port controller for controlling information transfer to and from said plurality of storage units while said cache communications switch is in the debug mode, said debug port controller coupled to said communications switch via one of said at least one debug port.