Single wire serial interface with addressing, Io, and multiplexing capability

A method for controlling a device, the method comprising:

• toggling an input signal to the device to transmit a register address as a series of clock pulses where the number of clock pulses exceeds a first predefined boundary value;
• maintaining the input signal in a logical high state for a duration that exceeds a predefined timeout period;
• and
• toggling the input signal to the device to transmit register data as a series of clock pulses where the number of clock pulses is less than or equal to the first predefined boundary value;
• and
• returning the input signal to the logical high state for a duration that exceeds a predefined timeout period.

A method for controlling a device, the method comprising:

• sending a repeating interleaved pattern of control values to the device, where each control value in the sequence corresponds to where each value is sent by:
• toggling an input signal to the device to transmit the control value being sent, where the control value being sent is encoded as a series of clock pulses;
• and
• maintaining the input signal in a logical high state for a duration that exceeds a predefined timeout period.

An interface for controlling a device, the interface comprising:

• a counter for accumulating a count of clock pulses encoded in a received signal;
• a register address latch;
• a first circuit configured to cause the accumulated count of clock pulses to be stored in the register address latch when the count of clock pulses exceeds a predefined boundary value;
• and
• a second circuit configured to cause the accumulated count of clock pulses to be stored in a register selected by the contents of the register address latch, when the input signal has been asserted in a logical high condition for a time that exceeds a predetermined timeout value.

An interface for controlling a device, the interface comprising:

• a counter for accumulating a count of clock pulses encoded in a received signal;
• a circuit configured to:
• cause the accumulated count of clock pulses to be sent to a target destination when the input signal has been asserted in a logical high condition for a time that exceeds a predetermined timeout value, where the target destination is based on a currently selected state in a series of states;
• and
• select a new currently selected state.